| Example |
/* NAND Device Driver Control Block */
NAND_DRV nand0_drv = {
Init,
UnInit,
PageRead,
PageWrite,
BlockErase
};
static U32 PageRead (U32 row, U8 *buf, NAND_DRV_CFG *cfg) {
U32 i, sec, ecc;
U32 *p = (U32 *)buf;
MLC_CMD = NAND_CMD_READ1ST; /* Read command (1st cycle) */
if (cfg->PageSize > 528) {
MLC_CMD = NAND_CMD_READ2ND; /* Read command (2nd cycle) */
}
SetAddr (row << 8, cfg->AddrCycles); /* Set address */
ecc = ECC_NOERR;
for (sec = 0; sec < cfg->SectorsPerPage; sec++) {
MLC_ECC_AUTO_DEC_REG = 0x00; /* Auto Decode */
if (!StatusFlag (NAND_CON_READY)) { /* Wait for controller ready */
return ERR_NAND_HW_TOUT;
}
if (!StatusFlag (NAND_ECC_READY)) { /* Wait for ECC ready */
return ERR_NAND_HW_TOUT;
}
if (MLC_ISR & NAND_ERR_DET) { /* Check for decode error */
ecc |= ECC_CORRECTED;
}
if (MLC_ISR & NAND_DEC_FAIL) {
ecc |= ECC_UNCORRECTED;
}
for (i = 0; i < (528 >> 2); i++) {
*p++ = MLC_BUFFX (i); /* Read main + spare area */
}
}
if (ecc & ECC_UNCORRECTED) {
return ERR_ECC_UNCOR; /* ECC could not correct the error */
}
if (ecc & ECC_CORRECTED) {
return ERR_ECC_COR; /* ECC corrected the data within page */
}
return RTV_NOERR;
}
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