| Example |
/* NAND Device Driver Control Block */
NAND_DRV nand0_drv = {
Init,
UnInit,
PageRead,
PageWrite,
BlockErase
};
static U32 BlockErase (U32 row, NAND_DRV_CFG *cfg) {
if (!StatusFlag (NAND_CON_READY)) { /* Wait for controller ready */
return ERR_NAND_HW_TOUT;
}
MLC_CMD = NAND_CMD_ERASE1ST; /* Erase command 1 */
SetAddr (row, cfg->AddrCycles); /* Set address */
MLC_CMD = NAND_CMD_ERASE2ND; /* Erase command 2 */
if (!StatusFlag (NAND_CON_READY)) { /* Wait for controller ready */
return ERR_NAND_HW_TOUT;
}
if (!StatusFlag (NAND_CHIP_BUSY)) { /* Wait while NAND busy */
return ERR_NAND_HW_TOUT;
}
MLC_CMD = NAND_CMD_STATUS; /* Write Read Status command */
if ((U8)MLC_DATAX(0) & NAND_STAT_FAIL) { /* Check if command successful */
return ERR_NAND_ERASE; /* Block Erase Failed */
}
return RTV_NOERR;
}
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