MPS - Microcontroller Prototyping System

Keil MPS Block Diagram (click on image for larger diagram).

Features

• Cortex-M0, Cortex-M1, Cortex-M3, or Cortex-M4 processor operating at up to 50MHz in FPGA
• Two Altera Stratix III EP3SL50 FPGAs
  - CPU FPGA: encrypted FPGA containing the processor, memory subsystem, UART, and debug & trace interfaces
  - DUT FPGA: holds users hardware implementation including 3rd party IP
  
• ARM PrimeCells and AMBA Design Kit (ADK) components implemented in the DUT FPGA
  - PL011 UART (x3)
  - PL022 Synchronous Serial Port
  - PL031 Real Time Clock
  - PL041 AC97 Advanced Audio CODEC Interface
  - PL181 MultiMedia Card Interface
  - SP804 Dual Timer (x2)
  - SP805 Watchdog
  
• 8MB Zero wait state SSRAM (50MHz)
• 64MB NOR Flash for software and non volatile storage (50MHz)
• 10/100Mbps Ethernet Phy
  - Requires user MAC IP implementation in DUT FPGA
• CAN, Flexray, and LIN Phys
  - Require user controller IP in DUT FPGA
• USB 2.0 High Speed - USB Device, USB Host, and USB-OTG
  - via AHB bus
• Serial Interfaces
  - 2 fixed UARTs
  - 2 configurable as either UART, CAN, FlexRay, or LIN
  
• DVI-A video support for up to 1280x1024 resolution
  - Requires user controller IP in DUT FPGA
• MMC/SD Card controller (PL181)
• AC97 Audio CODEC (PL041) supporting Line-in, Line-out, and internal speaker
• 2x20 Character LCD display plus user buttons and LEDs
• JTAG and Serial Wire debug modes
• Serial Wire Viewer and ETM Trace (Cortex-M3 only)
• Peripheral expansion using a range of Hpe v2 childboards available from Gleichmann Research