Restrictions

The µVision3 Logic Analyzer allows you to record changes of:

• global program variables including struct members.
• VTREGs that represent I/O pins of the microcontroller.
• Peripheral Registers (or SFR) that are triggered by external or internal events (see restriction below).

The Logic Analyzer allows you to define up to 255 different items and records the changes in a FIFO buffer that holds a total 65536 frames (for all items).

With the Logic Analyzer you cannot record the following items:

• Automatic variables defined inside a function
  Automatic variables are located on the stack or in overlayable memory regions. It is impossible to record changes of dynamic memory locations.
• Changes of CPU Registers
  CPU registers cannot be triggered with read or write breakpoints. Therefore such changes cannot be recorded.
• Peripheral Registers (or SFR) that represent timer registers
  Increments of timers (or similar peripherals) are not simulated. Instead the timing of events which are triggered by a timer is calculated. Therefore it impossible to view timer increments.
• I/O pins of communication peripherals
  I/O pin toggling of UART, CAN, SPI, or I²C communication peripherals is not simulated. It is assumed that the timing of communication streams is according the specifications. Instead the I/O stream is represented by VTREGs.
• Memory BUS Signals
  µVision simulates a CPU including memory areas, but it does not simulate the Memory BUS signals (data BUS, address BUS, and control lines like RD, WR, ALE). Therefore it is impossible to view memory BUS signals with the Logic Analyzer.