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RealView Compiler User's Guide

RealView® Compilation Tools for μVision Compiler User GuideVersion 3.1
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RealView® Compilation Tools for μVision Compiler User Guide

Version 3.1

Copyright © 2007 ARM Limited. All rights reserved.

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarks owned by ARM Limited. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision AMay 2007
Release for RVCT for mVision v3.1

Table of Contents

Preface
About this book
Intended audience
Using this book
Typographical conventions
Further reading
Feedback
Feedback on RealView Compilation Tools
Feedback on this book
1. Introduction
1.1. About the ARM compiler
1.2. Source language modes
1.3. The C and C++ libraries
1.4. New features of C99
1.4.1. Language features
1.4.2. Library features
2. Getting started with the ARM Compiler
2.1. Using command-line options
2.1.1. Invoking the ARM compiler
2.1.2. Ordering command-line options
2.1.3. Specifying command-line options with an environment variable
2.1.4. Autocompleting command-line options
2.1.5. Reading compiler options from a file
2.1.6. Specifying keyboard input
2.2. File naming conventions
2.2.1. Portability
2.2.2. Output files
2.3. Include files
2.3.1. The current place
2.3.2. The RVCT31INC environment variable
2.3.3. The search path
2.3.4. The TMP and TMPDIR environment variables
2.4. Precompiled header files
2.4.1. Automatic PCH processing
2.4.2. Manual PCH processing
2.4.3. Controlling the output of messages during PCH processing
2.4.4. Performance issues
2.5. Specifying the procedure call standard (AAPCS)
2.5.1. Interworking qualifiers
2.5.2. Position independence qualifiers
2.6. Using linker feedback
2.7. Thread-local storage
2.8. Eight‑byte alignment features
3. Compiler Features
3.1. Intrinsics
3.1.1. About intrinsics
3.1.2. Instruction intrinsics
3.1.3. ETSI basic operations
3.1.4. TI C55x intrinsics
3.1.5. Named register variables
3.2. Pragmas
4. Coding Practices
4.1. Optimizing code
4.1.1. Optimizing for size versus speed
4.1.2. Optimization levels and the debug view
4.1.3. Selecting the target device
4.1.4. Optimizing loops
4.1.5. Using volatile
4.2. Code metrics
4.2.1. Measuring code and data sizes
4.2.2. Measuring stack use
4.2.3. Reducing debug information in objects and libraries
4.3. Functions
4.3.1. Minimizing parameter passing overhead
4.3.2. __value_in_regs
4.3.3. __pure
4.3.4. Placing ARM function qualifiers
4.4. Inlining
4.4.1. How the compiler decides to inline
4.4.2. When is it practical for the compiler to inline?
4.4.3. Managing inlining
4.4.4. Inlining functions across multiple files
4.4.5. Debugging data and the --[no]_inline keyword
4.4.6. Marking functions as static
4.4.7. Setting breakpoints on inlined functions in ROM images
4.5. Aligning data
4.5.1. About data alignment
4.5.2. The __packed qualifier and unaligned accesses to data
4.5.3. __packed structures versus individually __packed fields
4.6. Using floating-point arithmetic
4.6.1. Support for floating-point operations
4.6.2. VFP architectures
4.6.3. The --fpu option
4.6.4. Floating-point linkage
4.6.5. The --fpmode option
4.6.6. Using the --fpu option
4.6.7. VFP support
4.7. Trapping and identifying division-by-zero errors
4.7.1. Integer division
4.7.2. (Software) Floating point division
4.8. Support for ARM architecture v6
4.8.1. Instruction generation
4.8.2. Alignment support
4.8.3. Endian support
5. Diagnostic Messages
5.1. Redirecting diagnostics
5.2. Severity of diagnostic messages
5.3. Controlling the output of diagnostic messages
5.4. Changing the severity of diagnostic messages
5.5. Suppressing diagnostic messages
5.6. Prefix letters in diagnostic messages
5.7. Suppressing warning messages with ‑W
5.8. Exit status codes and termination messages
5.8.1. Response to signals
5.8.2. Exit status
5.9. Data flow warnings
6. Using the Inline and Embedded Assemblers
6.1. Inline assembler
6.1.1. Inline assembler syntax
6.1.2. Restrictions on inline assembly operations
6.1.3. Virtual registers
6.1.4. Constants
6.1.5. Instruction expansion
6.1.6. Condition flags
6.1.7. Operands
6.1.8. Function calls and branches
6.1.9. Labels
6.1.10. Differences from previous versions of the ARM C/C++ compilers
6.2. Embedded assembler
6.2.1. Embedded assembler syntax
6.2.2. Restrictions on embedded assembly
6.2.3. Differences between expressions in embedded assembly and C or C++
6.2.4. Generation of embedded assembly functions
6.2.5. The __cpp keyword
6.2.6. Manual overload resolution
6.2.7. Keywords for related base classes
6.2.8. Keywords for member function classes
6.2.9. Calling non‑static member functions
6.2.10. Differences from previous versions of the ARM C/C++ compilers
6.3. Legacy inline assembler that accesses sp, lr, or pc
6.3.1. Accessing sp (r13), lr (r14), and pc (r15) in legacy code
6.4. Differences between inline and embedded assembly code
A. Semihosting
A.1. About semihosting
A.1.1. What is semihosting?
A.1.2. The semihosting interface
A.2. Semihosting implementation
A.2.1. RealView ARMulator ISS
A.2.2. RealView ICE
A.2.3. Instruction Set System Model
A.2.4. RealMonitor
A.3. Semihosting operations
A.3.1. angel_SWIreason_EnterSVC (0x17)
A.3.2. angel_SWIreason_ReportException (0x18)
A.3.3. SYS_CLOSE (0x02)
A.3.4. SYS_CLOCK (0x10)
A.3.5. SYS_ELAPSED (0x30)
A.3.6. SYS_ERRNO (0x13)
A.3.7. SYS_FLEN (0x0C)
A.3.8. SYS_GET_CMDLINE (0x15)
A.3.9. SYS_HEAPINFO (0x16)
A.3.10. SYS_ISERROR (0x08)
A.3.11. SYS_ISTTY (0x09)
A.3.12. SYS_OPEN (0x01)
A.3.13. SYS_READ (0x06)
A.3.14. SYS_READC (0x07)
A.3.15. SYS_REMOVE (0x0E)
A.3.16. SYS_RENAME (0x0F)
A.3.17. SYS_SEEK (0x0A)
A.3.18. SYS_SYSTEM (0x12)
A.3.19. SYS_TICKFREQ (0x31)
A.3.20. SYS_TIME (0x11)
A.3.21. SYS_TMPNAM (0x0D)
A.3.22. SYS_WRITE (0x05)
A.3.23. SYS_WRITEC (0x03)
A.3.24. SYS_WRITE0 (0x04)
A.4. Debug agent interaction SVCs

List of Figures

A.1. Semihosting overview

List of Tables

2.1. Filename suffixes recognized by the ARM compiler
2.2. Include file search paths
4.1. C code for incrementing and decrementing loops
4.2. C Disassembly for incrementing and decrementing loops
4.3. C code for rolled and unrolled bit‑counting loops
4.4. Disassembly for rolled and unrolled bit‑counting loops
4.5. C code for nonvolatile and volatile buffer loops
4.6. Disassembly for nonvolatile and volatile buffer loop
4.7. C code for pure and impure functions
4.8. Disassembly for pure and impure functions
4.9. C code for an unpacked struct, a packed struct, and a struct with individually packed fields
4.10. Disassembly for an unpacked struct, a packed struct, and a struct with individually packed fields
4.11. VFP compiler options
4.12. Floating‑point models supported in RVCT
5.1. Severity of diagnostic messages
5.2. Identifying diagnostic messages
6.1. Differences between inline and embedded assembler
A.1. Hardware vector reason codes
A.2. Software reason codes
A.3. Value of mode

List of Examples

3.1. C implementation of saturated add operation
3.2. Setting bits in the APSR using a named register variable
4.1. Floating-point operations
4.2. Support for floating-point operations in software
4.3. Support for floating-point operations in hardware
4.4. Intercepting __aeabi_div0 using $Super$$ and $Sub$$
4.5. Division by zero error
4.6. Disassembly of division by zero error
6.1. String copy with embedded assembler
6.2. __asm function
6.3. __cpp(expr)
6.4. C++ casts
6.5. static_cast<B*>(p)
6.6. Calling a non‑virtual function
6.7. Calling a virtual function
6.8. Legacy inline assembly code using lr
A.1.
Copyright © 2007 ARM Limited. All rights reserved.ARM DUI 0375A
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