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Preface Overview of the Compiler Getting Started with the Compiler Compiler Features Compiler intrinsics Performance benefits of compiler intrinsics ARM assembler instruction intrinsics Generic intrinsics Compiler intrinsics for controlling IRQ and FIQ in Compiler intrinsics for inserting optimization bar Compiler intrinsics for inserting native instructi Compiler intrinsics for Digital Signal Processing Compiler support for European Telecommunications S Overflow and carry status flags for C and C++ code Texas Instruments (TI) C55x intrinsics for optimiz Compiler support for accessing registers using nam Pragmas recognized by the compiler Compiler and processor support for bit-banding Compiler type attribute, __attribute__((bitband)) --bitband compiler command-line option How the compiler handles bit-band objects placed o Compiler support for thread-local storage Compiler support for literal pools Compiler eight-byte alignment features Precompiled Header (PCH) files Automatic Precompiled Header (PCH) file processing Precompiled Header (PCH) file processing and the h Precompiled Header (PCH) file creation requirement Compilation with multiple Precompiled Header (PCH) Obsolete Precompiled Header (PCH) files Manually specifying the filename and location of a Selectively applying Precompiled Header (PCH) file Suppressing Precompiled Header (PCH) file processi Message output during Precompiled Header (PCH) pro Performance issues with Precompiled Header (PCH) f Default compiler options that are affected by opti Compiler Coding Practices Compiler Diagnostic Messages Using the Inline and Embedded Assemblers of the AR Compiler Command-line Options Language Extensions Compiler-specific Features C and C++ Implementation Details What is Semihosting? Via File Syntax Summary Table of GNU Language Extensions Standard C Implementation Definition Standard C++ Implementation Definition C and C++ Compiler Implementation Limits

Compiler intrinsics for controlling IRQ and FIQ interrupts

3.5 Compiler intrinsics for controlling IRQ and FIQ interrupts

The intrinsics __disable_irq, __enable_irq, __disable_fiq and __enable_fiq control IRQ and FIQ interrupts.

You cannot use these intrinsics to change any other CPSR bits, including the mode, state, and imprecise data abort setting. This means that the intrinsics can be used only if the processor is already in a privileged mode, because the control bits of the CPSR and SPSR cannot be changed in User mode.
These intrinsics are available for all processor architectures in both ARM and Thumb state, as follows:
  • If you are compiling for processors that support ARMv6 (or later), a CPS instruction is generated inline for these functions, for example:
        CPSID  i
  • If you are compiling for processors that support ARMv4 or ARMv5 in ARM state, the compiler inlines a sequence of MRS and MSR instructions, for example:
        MRS  r0, CPSR
        ORR  r0, r0, #0x80
        MSR  CPSR_c, r0
  • If you are compiling for processors that support ARMv4 or ARMv5 in Thumb state, or if --compatible is being used, the compiler calls a helper function, for example:
        BL    __ARM_disable_irq
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