|
|||||||||||
|
Technical Support Support Resources
Product Information |
A51: DEFINING NEW INSTRUCTIONS WITH MACROSInformation in this article applies to:
QUESTIONI am using the M8051TBO from Virtual IP Group. This CPU has an additional instruction, DEC DPTR. The opcode is 0A5h but the Keil assembler does not directly support it. Other IP cores like the Mentor M8051EW have additional instructions, too (Mentor uses opcode 0A5h for a MOVC @DPTR++,A instruction). How can I use such instructions in my assembler programs? ANSWERTo use chip-specific instructions, you may define a Macro that expands to the appropriate opcode. For example:
DEC_DPTR MACRO ; DEC DPTR instruction on M8051TBO
DB 0A5H ; op-code
ENDM
MOVCI MACRO ; MOVC @DPTR++,A instruction on M8051EW
DB 0A5H ; op-code
ENDM
These macros may be used as if they were assembler instructions. For example:
DEC_DPTR
MOVCI
MORE INFORMATION
SEE ALSOFORUM THREADSThe following Discussion Forum threads may provide information related to this topic. Last Reviewed: Sunday, October 29, 2006 | ||||||||||
|
|||||||||||
Arm’s Privacy Policy has been updated. By continuing to use our site, you consent to Arm’s Privacy Policy. Please review our Privacy Policy to learn more about our collection, use and transfers
of your data.