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µVISION DEBUGGER: MENTOR E8051EW SIMULATOR OPTIONS


Information in this article applies to:

  • µVision Version 3

QUESTION

The Mentor M8051EW core has certain configuration features. Is it possible to simulate with Keil µVision the MOVC @(DPTR++),A instruction, multiple DPTR registers, and the behaviour of the MEX1, MEX2, and MEX3 memory extension register?

ANSWER

Yes. The Simulation has additional options for the S8051.DLL that can be entered in µVision under Options - Debug - Simulator CPU DLL Parameter:

  • -m8051EW changes the behaviour of the opcode 0xA5 to MOVC @(DPTR++),A and enables the multiple DPTR registers. The simulator is expanded with the EO register located at SFR address 0xA2.
  • -mex enables the MEX1 (SFR 0x94), MEX2 (SFR 0x95), and MEX3 (SFR 0x96) memory extension registers. Depending on the settings of these memory extension registers, the MOVX and MOVC instruction will use the extended address range.

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Last Reviewed: Friday, November 12, 2004


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