 8051 Instruction Set Manual |
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| InstructionsThe following pages describe the 8051 instruction set. Instructions are listed in alphabetical order and each is divided into several sections: | Description | Describes the instruction's effect and describes any arguments. | | See Also | Names related instructions. | | Bytes | Lists the number of bytes required to encode the instruction. | | Cycles | Lists the number of instruction cycles required to execute the instruction. Note that there are 12 oscillator cycles to one instruction cycle on a standard 8051. | | Encoding | Lists the byte encoding for the instruction. | | Operation | Lists, step-by-step, the operations performed by the instruction. | | Example | Shows proper use of the instruction. |
Many instructions have required arguments that are described in the following table: | Argument | Description |
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| addr11 | An 11-bit address destination. This argument is used by ACALL and AJMP instructions. The target of the CALL or JMP must lie within the same 2K page as the first byte of the following instruction. | | addr16 | A 16-bit address destination. This argument is used by LCALL and LJMP instructions. | | bit | A direct addressed bit in internal data RAM or SFR memory. | | direct | An internal data RAM location (0-127) or SFR (128-255). | | immediate | A constant included in the instruction encoding. | | offset | A signed (two's complement) 8-bit offset (-128 to 127) relative to the first byte of the following instruction. | | @Ri | An internal data RAM location (0-255) addressed indirectly through R0 or R1. | | Rn | Register R0-R7. |
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