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Spansion S6E1A12C0A

The Spansion S6E1A12C0A is a 32-bit ARM Cortex-M0+ Core (r0p1) - Maximum operating frequency: 40 MHz - Nested Vectored Interrupt Controller (NVIC) - 24-bit System timer (Sys Tick) Bit Band operation - Compatible with Cortex-M3 bit band operation On-chip Memory - Up to 88 Kbyte Flash - 6 Kbyte SRAM Multi-function Serial Interface (Max 3chn) - Selectable from UART/CSIO/LIN/I2C DMA Controller (2chn) A/D Converter (Max: 8chn) - 12-bit A/D Converter Base Timer (Max: 4chn) - Operation mode: 16-bit PWM, 16-bit PPG, 16/32-bit reload, 16/32-bit PWC General-purpose I/O Port - Up to 37 fast general-purpose I/O ports Dual Timer (32/16-bit Down Counter) Quadrature Position/Revolution Counter (QPRC) Multi-function Timer Real-time Clock (RTC) Watch Counter External Interrupt Controller Unit - Up to 8 external interrupt input pins - Non-maskable interrupt (NMI) input pin Watchdog Timer (2 chn) Clock and Reset - 5 clock sources (2 ext. osc., 2 built-in CR osc, main PLL) - Reset sources: INITX Pins, POR, SW, Watchdog, LVD, CSV Clock Supervisor (CSV) - Ext. OSC clock failure (clock stop) detect - Ext. OSC frequency anomaly detect Low-voltage Detector (LVD) - LVD1: error reporting via interrupt - LVD2: auto-reset operation Low Power Consumption Mode - 4 low power consumption modes (SLEEP, TIMER, RTC, STOP) Peripheral Clock Gating Debug - Serial Wire Debug Port (SW-DP) - Micro Trace Buffer (MTB) Unique ID -41-bit unique value of the device has been set Power Supply - Wide voltage range: VCC = 2.7 V to 5.5 V.

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Development Tools
Compiler, Assembler, Linker, Debugger
JTAG Debuggers
Data Sheets
1,038,676 bytes
Generic User Guide
1,048,576 bytes
Technical Reference Manual
524,288 bytes

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Header Files
FLASH Utilities
Real-Time OS
Simulated Features
Simulation for this device is provided by the default peripheral simulation driver.

Complete peripheral simulation is not available and is not planned to be implemented by ARM.

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