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On-Line Manuals
8051 Instruction Set Manual
Architecture Overview
Memory Classes and Layout
Classic 8051
Classic 8051 Memory Layout
Extended 8051 Variants
Extended 8051 Memory Layout
NXP 80C51MX
NXP 80C51MX Memory Layout
251 Architecture
251 Memory Layout
CPU Registers
8051 Variants
251 Architecture
Program Status Word (PSW)
Opcodes
Instructions
8051 Variants
The classic 8051 provides 4 register banks of 8 registers each. These register banks are mapped into the DATA memory area at address 0 – 0x1F. In addition the CPU provides a 8-bit A (accumulator) and B register and a 16-bit DPTR (data pointer) for addressing XDATA and CODE memory. These registers are also mapped into the SFR space as special function registers.
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