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251 Architecture

The 251 architecture supports an extra 32 bytes of registers in addition to the 4 banks of 8 registers found in the classic 8051. To maintain 8051 register bank compatibility, the lower 8 byte registers are mapped to memory locations 00:00 - 00:0x1F. Unlike the 8051 registers, the additional 32 bytes of 251 registers are not banked and are not mapped to any memory locations.

The register file can be addressed in the following ways:

  • Register 0 - 15 can be addressed as byte, word, or double word (Dword) registers.
  • Register 16 - 31 can only be addressed as word or Dword registers.
  • Register DR56 and DR60 can only be addressed only as Dword registers.
  • There are 16 possible byte registers (R0 - R15), 16 possible word registers (WR0 - WR30) and 10 possible Dword registers (DR0 - DR28, DR56 - DR60) that can be addressed in any combination.
  • All Dword registers are Dword aligned; each is addressed as DRk with "k" being the lowest of the 4 consecutive registers. For example, DR4 consists of registers 4 - 7.
  • All word registers are word aligned; each is addressed as WRj with "j" being the lower of the 2 consecutive registers. For example, WR4 consists of registers 4 - 5.
  • All byte registers are byte aligned; each is addressed as Rm with "m" being the register number. For example, R4.

The following figure shows the register file format for the 251 microcontroller.

251 Registers

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