Infineon XMC4500-768

The Infineon XMC4500-768 is a CPU Core - High Performance 32-bit ARM Cortex-M4 CPU with FPU - 120 MHz maximum frequency - DSP/MAC instructions - System timer (SysTick) for Operating System support - Memory Protection Unit (MPU) - Nested Vectored Interrupt Controller - Two General Purpose DMA (DMA) with up-to 12 channels - Event Request Unit (ERU) for programmable processing of ext./int. service requests - Flexible CRC Engine (FCE) for multiple bit error detection On-Chip Memories - 16 KB boot ROM - 112 KB high-speed program memory - 64 KB high speed data memory - 32 KB high-speed communication - 1024 KB Flash Memory with 4 KB instruction cache Communication Peripherals - Ethernet MAC module (ETH0) capable of 10/100 Mbit/s transfer rates - Universal Serial Bus (USB), USB 2.0 host, Full-Speed, OTG, internal Phy - Controller Area Network interface (MultiCAN), Full-CAN/Basic-CAN with 3 nodes - Six Universal Serial Interface Channels (USIC), usable as UART, SPI, IIC, IIS, LIN interfaces - LED and Touch-Sense Controller (LEDTS) - SD and Multi-Media Card interface (SDMMC) - External Bus Interface Unit (EBU) Industrial Control Peripherals - Two Capture/Compare Units 8 (CCU8) - Four Capture/Compare Units 4 (CCU4) - Two Position Interfaces (POSIF) - Window Watchdog Timer (WDT) - Die Temperature Sensor (DTS) - Real Time Clock (RTC) - System Control Unit (SCU) Analog Frontend Peripherals - Four A/D Converters (VADC) of 12-bit resolution, 8 channels each - Delta Sigma Demodulator (DSD) with four channels - D/A Converter (DAC) with two channels of 12-bit resolution On-Chip Debug Support - Full support for debug features: 8 breakpoints, CoreSight, trace - ARM-JTAG, SWD, single wire trace Input/Output Lines - Programmable port driver control module (PORTS) - Individual bit addressability - Tri-stated in input mode - Push/pull or open drain output mode - Boundary scan test support over JTAG interface.