/****************************************************************************************************//** * @file XMC4500.h * * @brief CMSIS Cortex-M6 Peripheral Access Layer Header File for * XMC4500 from Infineon. * * @version V1.1.5.1 (Reference Manual v1.1) * @date 1. October 2012 * * @note Generated with SVDConv V2.77h (Header Version info manually edited) * from CMSIS SVD File 'XMC4500_Processed_SVD.xml' Version 1.1.5 (Reference Manual v1.1), *******************************************************************************************************/ /** @addtogroup Infineon * @{ */ /** @addtogroup XMC4500 * @{ */ #ifndef XMC4500_H #define XMC4500_H #ifdef __cplusplus extern "C" { #endif /* ------------------------- Interrupt Number Definition ------------------------ */ typedef enum { /* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */ BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ SysTick_IRQn = -1, /*!< 15 System Tick Timer */ /* --------------------- XMC4500 Specific Interrupt Numbers --------------------- */ SCU_0_IRQn = 0, /*!< 0 SCU_0 */ ERU0_0_IRQn = 1, /*!< 1 ERU0_0 */ ERU0_1_IRQn = 2, /*!< 2 ERU0_1 */ ERU0_2_IRQn = 3, /*!< 3 ERU0_2 */ ERU0_3_IRQn = 4, /*!< 4 ERU0_3 */ ERU1_0_IRQn = 5, /*!< 5 ERU1_0 */ ERU1_1_IRQn = 6, /*!< 6 ERU1_1 */ ERU1_2_IRQn = 7, /*!< 7 ERU1_2 */ ERU1_3_IRQn = 8, /*!< 8 ERU1_3 */ PMU0_0_IRQn = 12, /*!< 12 PMU0_0 */ VADC0_C0_0_IRQn = 14, /*!< 14 VADC0_C0_0 */ VADC0_C0_1_IRQn = 15, /*!< 15 VADC0_C0_1 */ VADC0_C0_2_IRQn = 16, /*!< 16 VADC0_C0_2 */ VADC0_C0_3_IRQn = 17, /*!< 17 VADC0_C0_3 */ VADC0_G0_0_IRQn = 18, /*!< 18 VADC0_G0_0 */ VADC0_G0_1_IRQn = 19, /*!< 19 VADC0_G0_1 */ VADC0_G0_2_IRQn = 20, /*!< 20 VADC0_G0_2 */ VADC0_G0_3_IRQn = 21, /*!< 21 VADC0_G0_3 */ VADC0_G1_0_IRQn = 22, /*!< 22 VADC0_G1_0 */ VADC0_G1_1_IRQn = 23, /*!< 23 VADC0_G1_1 */ VADC0_G1_2_IRQn = 24, /*!< 24 VADC0_G1_2 */ VADC0_G1_3_IRQn = 25, /*!< 25 VADC0_G1_3 */ VADC0_G2_0_IRQn = 26, /*!< 26 VADC0_G2_0 */ VADC0_G2_1_IRQn = 27, /*!< 27 VADC0_G2_1 */ VADC0_G2_2_IRQn = 28, /*!< 28 VADC0_G2_2 */ VADC0_G2_3_IRQn = 29, /*!< 29 VADC0_G2_3 */ VADC0_G3_0_IRQn = 30, /*!< 30 VADC0_G3_0 */ VADC0_G3_1_IRQn = 31, /*!< 31 VADC0_G3_1 */ VADC0_G3_2_IRQn = 32, /*!< 32 VADC0_G3_2 */ VADC0_G3_3_IRQn = 33, /*!< 33 VADC0_G3_3 */ DSD0_M_0_IRQn = 34, /*!< 34 DSD0_M_0 */ DSD0_M_1_IRQn = 35, /*!< 35 DSD0_M_1 */ DSD0_M_2_IRQn = 36, /*!< 36 DSD0_M_2 */ DSD0_M_3_IRQn = 37, /*!< 37 DSD0_M_3 */ DSD0_A_4_IRQn = 38, /*!< 38 DSD0_A_4 */ DSD0_A_5_IRQn = 39, /*!< 39 DSD0_A_5 */ DSD0_A_6_IRQn = 40, /*!< 40 DSD0_A_6 */ DSD0_A_7_IRQn = 41, /*!< 41 DSD0_A_7 */ DAC0_0_IRQn = 42, /*!< 42 DAC0_0 */ DAC0_1_IRQn = 43, /*!< 43 DAC0_1 */ CCU40_0_IRQn = 44, /*!< 44 CCU40_0 */ CCU40_1_IRQn = 45, /*!< 45 CCU40_1 */ CCU40_2_IRQn = 46, /*!< 46 CCU40_2 */ CCU40_3_IRQn = 47, /*!< 47 CCU40_3 */ CCU41_0_IRQn = 48, /*!< 48 CCU41_0 */ CCU41_1_IRQn = 49, /*!< 49 CCU41_1 */ CCU41_2_IRQn = 50, /*!< 50 CCU41_2 */ CCU41_3_IRQn = 51, /*!< 51 CCU41_3 */ CCU42_0_IRQn = 52, /*!< 52 CCU42_0 */ CCU42_1_IRQn = 53, /*!< 53 CCU42_1 */ CCU42_2_IRQn = 54, /*!< 54 CCU42_2 */ CCU42_3_IRQn = 55, /*!< 55 CCU42_3 */ CCU43_0_IRQn = 56, /*!< 56 CCU43_0 */ CCU43_1_IRQn = 57, /*!< 57 CCU43_1 */ CCU43_2_IRQn = 58, /*!< 58 CCU43_2 */ CCU43_3_IRQn = 59, /*!< 59 CCU43_3 */ CCU80_0_IRQn = 60, /*!< 60 CCU80_0 */ CCU80_1_IRQn = 61, /*!< 61 CCU80_1 */ CCU80_2_IRQn = 62, /*!< 62 CCU80_2 */ CCU80_3_IRQn = 63, /*!< 63 CCU80_3 */ CCU81_0_IRQn = 64, /*!< 64 CCU81_0 */ CCU81_1_IRQn = 65, /*!< 65 CCU81_1 */ CCU81_2_IRQn = 66, /*!< 66 CCU81_2 */ CCU81_3_IRQn = 67, /*!< 67 CCU81_3 */ POSIF0_0_IRQn = 68, /*!< 68 POSIF0_0 */ POSIF0_1_IRQn = 69, /*!< 69 POSIF0_1 */ POSIF1_0_IRQn = 70, /*!< 70 POSIF1_0 */ POSIF1_1_IRQn = 71, /*!< 71 POSIF1_1 */ CAN0_0_IRQn = 76, /*!< 76 CAN0_0 */ CAN0_1_IRQn = 77, /*!< 77 CAN0_1 */ CAN0_2_IRQn = 78, /*!< 78 CAN0_2 */ CAN0_3_IRQn = 79, /*!< 79 CAN0_3 */ CAN0_4_IRQn = 80, /*!< 80 CAN0_4 */ CAN0_5_IRQn = 81, /*!< 81 CAN0_5 */ CAN0_6_IRQn = 82, /*!< 82 CAN0_6 */ CAN0_7_IRQn = 83, /*!< 83 CAN0_7 */ USIC0_0_IRQn = 84, /*!< 84 USIC0_0 */ USIC0_1_IRQn = 85, /*!< 85 USIC0_1 */ USIC0_2_IRQn = 86, /*!< 86 USIC0_2 */ USIC0_3_IRQn = 87, /*!< 87 USIC0_3 */ USIC0_4_IRQn = 88, /*!< 88 USIC0_4 */ USIC0_5_IRQn = 89, /*!< 89 USIC0_5 */ USIC1_0_IRQn = 90, /*!< 90 USIC1_0 */ USIC1_1_IRQn = 91, /*!< 91 USIC1_1 */ USIC1_2_IRQn = 92, /*!< 92 USIC1_2 */ USIC1_3_IRQn = 93, /*!< 93 USIC1_3 */ USIC1_4_IRQn = 94, /*!< 94 USIC1_4 */ USIC1_5_IRQn = 95, /*!< 95 USIC1_5 */ USIC2_0_IRQn = 96, /*!< 96 USIC2_0 */ USIC2_1_IRQn = 97, /*!< 97 USIC2_1 */ USIC2_2_IRQn = 98, /*!< 98 USIC2_2 */ USIC2_3_IRQn = 99, /*!< 99 USIC2_3 */ USIC2_4_IRQn = 100, /*!< 100 USIC2_4 */ USIC2_5_IRQn = 101, /*!< 101 USIC2_5 */ LEDTS0_0_IRQn = 102, /*!< 102 LEDTS0_0 */ FCE0_0_IRQn = 104, /*!< 104 FCE0_0 */ GPDMA0_0_IRQn = 105, /*!< 105 GPDMA0_0 */ SDMMC0_0_IRQn = 106, /*!< 106 SDMMC0_0 */ USB0_0_IRQn = 107, /*!< 107 USB0_0 */ ETH0_0_IRQn = 108, /*!< 108 ETH0_0 */ GPDMA1_0_IRQn = 110 /*!< 110 GPDMA1_0 */ } IRQn_Type; /** @addtogroup Configuration_of_CMSIS * @{ */ /* ================================================================================ */ /* ================ Processor and Core Peripheral Section ================ */ /* ================================================================================ */ /* ----------------Configuration of the cm4 Processor and Core Peripherals---------------- */ #define __CM4_REV 0x0200 /*!< Cortex-M4 Core Revision */ #define __MPU_PRESENT 1 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 6 /*!< Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ #define __FPU_PRESENT 1 /*!< FPU present or not */ /** @} */ /* End of group Configuration_of_CMSIS */ #include /*!< Cortex-M4 processor and core peripherals */ #include "system_XMC4500.h" /*!< XMC4500 System */ /* ================================================================================ */ /* ================ Device Specific Peripheral Section ================ */ /* ================================================================================ */ /* Macro to modify desired bitfields of a register */ #define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & mask) | \ (reg & ((uint32_t)~((uint32_t)mask))) /* Macro to modify desired bitfields of a register */ #define WR_REG_SIZE(reg, mask, pos, val, size) { \ uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \ uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \ uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \ uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \ reg = (uint##size##_t) (VAL2 | VAL4);\ } /** Macro to read bitfields from a register */ #define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos) /** Macro to read bitfields from a register */ #define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \ (uint32_t)mask) >> pos) ) /** Macro to set a bit in register */ #define SET_BIT(reg, pos) (reg |= ((uint32_t)1<