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Nuvoton NUC122SC1AN

The Nuvoton NUC122SC1AN is a + Core - ARM Cortex-M0 core runs up to 60MHz. - NVIC for the 32 interrupt inputs, each with 4-levels of priority. - Serial Wire Debug supports with 2 watchpoints/4 breakpoints. + Widely operating voltage range from 2.5V to 5.5V + Flash EPROM Memory - 32K/64K bytes Flash EPROM for program code. - 4kB flash for ISP loader - Support ISP/IAP program code update - Support 2 wire In Circuit Program (ICP) function to update code through SWD/ICE interface - Support fast parallel programming mode by external programmer + SRAM Memory - 4K/8K bytes embedded SRAM. + Clock Control - Build-in 22.1184 MHz OSC (Trimmed to 3%) for system operation - Low Speed 10KHz OSC for watchdog and wakeup sleep operation. - Support one PLL, up to 60MHz, for high performance system operation. - External 4~24 MHz crystal input for USB and precise timing operating. - External 32 kHz crystal input for RTC function and low power system operation. + GPIO - Four I/O modes (bi-direction, Push-Pull, Open-Drain, IN high impendence) + Timers - 4 sets of 32-bit timer with 24-bit counters and one 8-bit pre-scaler. + Watch Dog Timer + RTC + PWM/Capture - up to two 16-bit PWM generators. - Up to four 16-bit digital Capture timers. - Support Capture interrupt + UART - Two UART controllers - Support IrDA(SIR) function - Support RS-485 9-bit mode and direction control + SPI - Up to two sets of SPI device. - Master up to 20 MHz / Slave up to 10 MHz. + I2C - One set of I2C device. - Master/Slave up to 1Mbit/s. + USB 2.0 Full-Speed Device - Support Control, Bulk In/Out, Interrupt and Isochronous transfers. - Provide 6 programmable endpoints. + Brown-out detector - with 4 levels: 4.5V/3.8V/2.7V/2.4V + One built-in LDO.

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Development Tools
Compiler, Assembler, Linker, Debugger
JTAG Debuggers
Data Sheets
Generic User Guide
953,546 bytes
Reference Manual
5,041,273 bytes
Technical Reference Manual
472,236 bytes

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Header Files
FLASH Utilities
Real-Time OS
Simulated Features
Simulation for this device is provided by the default peripheral simulation driver.

Complete peripheral simulation is not available and is not planned to be implemented by ARM.

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