/*---------------------------------------------------------------------------------------------------------*/
/* */
/* Copyright (c) Nuvoton Technology Corp. All rights reserved. */
/* */
/*---------------------------------------------------------------------------------------------------------*/
#ifndef __NUC122_H__
#define __NUC122_H__
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
typedef enum IRQn
{
/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
/************************ NUC102 Interrupt Numbers ************************************************/
BOD_IRQn = 0,
WDT_IRQn = 1,
EINT0_IRQn = 2,
EINT1_IRQn = 3,
GPAB_IRQn = 4,
GPCD_IRQn = 5,
PWMA_IRQn = 6,
PWMB_IRQn = 7,
TMR0_IRQn = 8,
TMR1_IRQn = 9,
TMR2_IRQn = 10,
TMR3_IRQn = 11,
UART0_IRQn = 12,
UART1_IRQn = 13,
SPI0_IRQn = 14,
SPI1_IRQn = 15,
SPI2_IRQn = 16,
SPI3_IRQn = 17,
I2C0_IRQn = 18,
I2C1_IRQn = 19,
CAN0_IRQn = 20,
CAN1_IRQn = 21,
SD_IRQn = 22,
USBD_IRQn = 23,
PS2_IRQn = 24,
ACMP_IRQn = 25,
PDMA_IRQn = 26,
I2S_IRQn = 27,
PWRWU_IRQn = 28,
ADC_IRQn = 29,
DAC_IRQn = 30,
RTC_IRQn = 31
} IRQn_Type;
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/* Configuration of the Cortex-M0 Processor and Core Peripherals */
#define __MPU_PRESENT 0 /*!< armikcmu does not provide a MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< armikcmu Supports 2 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
#include "system_NUC122.h" /* NUC122 System */
#include "System\SysInfra.h"
/******************************************************************************/
/* Device Specific Peripheral registers structures */
/******************************************************************************/
/*--------------------- General Purpose Input and Ouptut ---------------------*/
typedef struct
{
__IO uint32_t PMD0:2;
__IO uint32_t PMD1:2;
__IO uint32_t PMD2:2;
__IO uint32_t PMD3:2;
__IO uint32_t PMD4:2;
__IO uint32_t PMD5:2;
__IO uint32_t PMD6:2;
__IO uint32_t PMD7:2;
__IO uint32_t PMD8:2;
__IO uint32_t PMD9:2;
__IO uint32_t PMD10:2;
__IO uint32_t PMD11:2;
__IO uint32_t PMD12:2;
__IO uint32_t PMD13:2;
__IO uint32_t PMD14:2;
__IO uint32_t PMD15:2;
} GPIO_PMD_T;
typedef __IO uint32_t GPIO_OFFD_T;
typedef __IO uint32_t GPIO_DOUT_T;
typedef __IO uint32_t GPIO_DMASK_T;
typedef __IO uint32_t GPIO_PIN_T;
typedef __IO uint32_t GPIO_DBEN_T;
typedef __IO uint32_t GPIO_IMD_T;
typedef __IO uint32_t GPIO_IEN_T;
typedef __IO uint32_t GPIO_ISRC_T;
typedef struct
{
union {
__IO uint32_t u32PMD;
struct {
__IO uint32_t PMD0:2;
__IO uint32_t PMD1:2;
__IO uint32_t PMD2:2;
__IO uint32_t PMD3:2;
__IO uint32_t PMD4:2;
__IO uint32_t PMD5:2;
__IO uint32_t PMD6:2;
__IO uint32_t PMD7:2;
__IO uint32_t PMD8:2;
__IO uint32_t PMD9:2;
__IO uint32_t PMD10:2;
__IO uint32_t PMD11:2;
__IO uint32_t PMD12:2;
__IO uint32_t PMD13:2;
__IO uint32_t PMD14:2;
__IO uint32_t PMD15:2;
} PMD;
};
union {
__IO uint32_t u32OFFD;
__IO uint32_t OFFD;
};
union {
__IO uint32_t u32DOUT;
__IO uint32_t DOUT;
};
union {
__IO uint32_t u32DMASK;
__IO uint32_t DMASK;
};
union {
__IO uint32_t u32PIN;
__IO uint32_t PIN;
};
union {
__IO uint32_t u32DBEN;
__IO uint32_t DBEN;
};
union {
__IO uint32_t u32IMD;
__IO uint32_t IMD;
};
union {
__IO uint32_t u32IEN;
__IO uint32_t IEN;
};
union {
__IO uint32_t u32ISRC;
__IO uint32_t ISRC;
};
} GPIO_T;
typedef struct
{
union {
__IO uint32_t u32DBNCECON;
struct {
__IO uint32_t DBCLKSEL:4;
__IO uint32_t DBCLKSRC:1;
__IO uint32_t ICLK_ON:1;
__I uint32_t RESERVE:26;
} DBNCECON;
};
} GPIO_DBNCECON_T;
/* GPIO PMD Bit Field Definitions */
#define GPIO_PMD_PMD15_Pos 30
#define GPIO_PMD_PMD15_Msk (0x3ul << GPIO_PMD_PMD15_Pos)
#define GPIO_PMD_PMD14_Pos 28
#define GPIO_PMD_PMD14_Msk (0x3ul << GPIO_PMD_PMD14_Pos)
#define GPIO_PMD_PMD13_Pos 26
#define GPIO_PMD_PMD13_Msk (0x3ul << GPIO_PMD_PMD13_Pos)
#define GPIO_PMD_PMD12_Pos 24
#define GPIO_PMD_PMD12_Msk (0x3ul << GPIO_PMD_PMD12_Pos)
#define GPIO_PMD_PMD11_Pos 22
#define GPIO_PMD_PMD11_Msk (0x3ul << GPIO_PMD_PMD11_Pos)
#define GPIO_PMD_PMD10_Pos 20
#define GPIO_PMD_PMD10_Msk (0x3ul << GPIO_PMD_PMD10_Pos)
#define GPIO_PMD_PMD9_Pos 18
#define GPIO_PMD_PMD9_Msk (0x3ul << GPIO_PMD_PMD9_Pos)
#define GPIO_PMD_PMD8_Pos 16
#define GPIO_PMD_PMD8_Msk (0x3ul << GPIO_PMD_PMD8_Pos)
#define GPIO_PMD_PMD7_Pos 14
#define GPIO_PMD_PMD7_Msk (0x3ul << GPIO_PMD_PMD7_Pos)
#define GPIO_PMD_PMD6_Pos 12
#define GPIO_PMD_PMD6_Msk (0x3ul << GPIO_PMD_PMD6_Pos)
#define GPIO_PMD_PMD5_Pos 10
#define GPIO_PMD_PMD5_Msk (0x3ul << GPIO_PMD_PMD5_Pos)
#define GPIO_PMD_PMD4_Pos 8
#define GPIO_PMD_PMD4_Msk (0x3ul << GPIO_PMD_PMD4_Pos)
#define GPIO_PMD_PMD3_Pos 6
#define GPIO_PMD_PMD3_Msk (0x3ul << GPIO_PMD_PMD3_Pos)
#define GPIO_PMD_PMD2_Pos 4
#define GPIO_PMD_PMD2_Msk (0x3ul << GPIO_PMD_PMD2_Pos)
#define GPIO_PMD_PMD1_Pos 2
#define GPIO_PMD_PMD1_Msk (0x3ul << GPIO_PMD_PMD1_Pos)
#define GPIO_PMD_PMD0_Pos 0
#define GPIO_PMD_PMD0_Msk (0x3ul << GPIO_PMD_PMD0_Pos)
/* GPIO OFFD Bit Field Definitions */
#define GPIO_OFFD_Pos 16
#define GPIO_OFFD_Msk (0xFFFFul << GPIO_OFFD_Pos)
/* GPIO DOUT Bit Field Definitions */
#define GPIO_DOUT_Pos 0
#define GPIO_DOUT_Msk (0xFFFFul << GPIO_DOUT_Pos)
/* GPIO DMASK Bit Field Definitions */
#define GPIO_DMASK_Pos 0
#define GPIO_DMASK_Msk (0xFFFFul << GPIO_DMASK_Pos)
/* GPIO PIN Bit Field Definitions */
#define GPIO_PIN_Pos 0
#define GPIO_PIN_Msk (0xFFFFul << GPIO_PIN_Pos)
/* GPIO DBEN Bit Field Definitions */
#define GPIO_DBEN_Pos 0
#define GPIO_DBEN_Msk (0xFFFFul << GPIO_DBEN_Pos)
/* GPIO IMD Bit Field Definitions */
#define GPIO_IMD_Pos 0
#define GPIO_IMD_Msk (0xFFFFul << GPIO_IMD_Pos)
/* GPIO IEN Bit Field Definitions */
#define GPIO_IEN_IR_EN_Pos 16
#define GPIO_IEN_IR_EN_Msk (0xFFFFul << GPIO_IEN_IR_EN_Pos)
#define GPIO_IEN_IF_EN_Pos 0
#define GPIO_IEN_IF_EN_Msk (0xFFFFul << GPIO_IEN_IF_EN_Pos)
/* GPIO ISRC Bit Field Definitions */
#define GPIO_ISRC_Pos 0
#define GPIO_ISRC_Msk (0xFFFFul << GPIO_ISRC_Pos)
/* GPIO DBNCECON Bit Field Definitions */
#define GPIO_DBNCECON_ICLK_ON_Pos 5
#define GPIO_DBNCECON_ICLK_ON_Msk (1ul << GPIO_DBNCECON_ICLK_ON_Pos)
#define GPIO_DBNCECON_DBCLKSRC_Pos 4
#define GPIO_DBNCECON_DBCLKSRC_Msk (1ul << GPIO_DBNCECON_DBCLKSRC_Pos)
#define GPIO_DBNCECON_DBCLKSEL_Pos 0
#define GPIO_DBNCECON_DBCLKSEL_Msk (0xFul << GPIO_DBNCECON_DBCLKSEL_Pos)
/* GPIO Port[x] Pin I/O Bit Output/Input Control Bit Field Definitions */
#define GPIO_GPIOx_DOUT_Pos 0
#define GPIO_GPIOx_DOUT_Msk (1ul << GPIO_GPIOx_DOUT_Pos)
/*------------------------- UART Interface Controller ------------------------*/
typedef __IO uint32_t UART_DATA_T;
typedef struct
{
__IO uint32_t RDA_IEN:1;
__IO uint32_t THRE_IEN:1;
__IO uint32_t RLS_IEN:1;
__IO uint32_t MODEM_IEN:1;
__IO uint32_t RTO_IEN:1;
__IO uint32_t BUF_ERR_IEN:1;
__IO uint32_t WAKE_IEN:1;
__I uint32_t RESERVE0:1;
__IO uint32_t LIN_RX_BRK_IEN:1;
__I uint32_t RESERVE1:2;
__IO uint32_t TIME_OUT_EN:1; /* Time-out counter enable */
__IO uint32_t AUTO_RTS_EN:1;
__IO uint32_t AUTO_CTS_EN:1;
__IO uint32_t DMA_TX_EN:1;
__IO uint32_t DMA_RX_EN:1;
__I uint32_t RESERVE2:16;
} UART_IER_T;
typedef struct
{
__I uint32_t RESERVE0:1;
__IO uint32_t RFR:1;
__IO uint32_t TFR:1;
__I uint32_t RESERVE1:1;
__IO uint32_t RFITL:4; /* Rx FIFO Interrupt Trigger Level */
__IO uint32_t RX_DIS:1;
__I uint32_t RESERVE2:7;
__IO uint32_t RTS_TRI_LEVEL:4;
__I uint32_t RESERVE3:12;
} UART_FCR_T;
typedef struct
{
__IO uint32_t WLS:2; /* Word length select */
__IO uint32_t NSB:1; /* Number of STOP bit */
__IO uint32_t PBE:1; /* Parity bit enable */
__IO uint32_t EPE:1; /* Even parity enable */
__IO uint32_t SPE:1; /* Stick parity enable*/
__IO uint32_t BCB:1; /* Break control bit */
__I uint32_t RESERVE:25;
} UART_LCR_T;
typedef struct
{
__I uint32_t RESERVE0:1;
__IO uint32_t RTS:1;
__I uint32_t RESERVE1:2;
__IO uint32_t LBME:1;
__I uint32_t RESERVE2:4;
__IO uint32_t LEV_RTS:1;
__I uint32_t RESERVE3:3;
__I uint32_t RTS_ST:1; /* RTS status */
__I uint32_t RESERVE4:18;
} UART_MCR_T;
typedef struct
{
__IO uint32_t DCTSF:1;
__I uint32_t RESERVE0:3;
__I uint32_t CTS_ST:1; /* CTS status */
__I uint32_t RESERVE1:3;
__IO uint32_t LEV_CTS:1;
__I uint32_t RESERVE2:23;
} UART_MSR_T;
typedef struct
{
__IO uint32_t RX_OVER_IF:1;
__I uint32_t RESERVE0:2;
__IO uint32_t RS485_ADD_DETF:1;
__IO uint32_t PEF:1;
__IO uint32_t FEF:1;
__IO uint32_t BIF:1;
__I uint32_t RESERVE1:1;
__I uint32_t RX_POINTER:6;
__I uint32_t RX_EMPTY:1;
__I uint32_t RX_FULL:1;
__I uint32_t TX_POINTER:6;
__I uint32_t TX_EMPTY:1;
__I uint32_t TX_FULL:1;
__IO uint32_t TX_OVER_IF:1;
__I uint32_t RESERVE2:3;
__I uint32_t TE_FLAG:1; /* Transmitter empty flag */
__I uint32_t RESERVE3:3;
} UART_FSR_T;
typedef struct
{
__IO uint32_t RDA_IF:1;
__IO uint32_t THRE_IF:1;
__IO uint32_t RLS_IF:1;
__IO uint32_t MODEM_IF:1;
__IO uint32_t TOUT_IF:1;
__IO uint32_t BUF_ERR_IF:1;
__I uint32_t RESERVE0:1;
__IO uint32_t LIN_RX_BREAK_IF:1;
__IO uint32_t RDA_INT:1;
__IO uint32_t THRE_INT:1;
__IO uint32_t RLS_INT:1;
__IO uint32_t MODEM_INT:1;
__IO uint32_t TOUT_INT:1;
__IO uint32_t BUF_ERR_INT:1;
__I uint32_t RESERVE1:1;
__IO uint32_t LIN_Rx_Break_INT:1;
__I uint32_t RESERVE2:2;
__IO uint32_t HW_RLS_IF:1;
__IO uint32_t HW_MODEM_IF:1;
__IO uint32_t HW_TOUT_IF:1;
__IO uint32_t HW_BUF_ERR_IF:1;
__IO uint32_t RESERVE3:1;
__IO uint32_t HW_LIN_RX_BREAK_IF:1;
__I uint32_t RESERVE4:2;
__IO uint32_t HW_RLS_INT:1;
__IO uint32_t HW_MODEM_INT:1;
__IO uint32_t HW_TOUT_INT:1;
__IO uint32_t HW_BUF_ERR_INT:1;
__IO uint32_t RESERVE5:1;
__IO uint32_t HW_LIN_RX_BREAK_INT:1;
} UART_ISR_T;
typedef struct
{
__IO uint32_t TOIC:8;
__IO uint32_t DLY:8;
__I uint32_t RESERVE1:16;
} UART_TOR_T;
typedef struct
{
__IO uint32_t BRD:16;
__I uint32_t RESERVE0:8;
__IO uint32_t DIVIDER_X:4;
__IO uint32_t DIV_X_ONE:1;
__IO uint32_t DIV_X_EN:1;
__I uint32_t RESERVE1:2;
} UART_BAUD_T;
typedef struct
{
__I uint32_t RESERVE0:1;
__IO uint32_t TX_SELECT:1;
__I uint32_t RESERVE1:3;
__IO uint32_t INV_TX:1;
__IO uint32_t INV_RX:1;
__I uint32_t RESERVE2:25;
} UART_IRCR_T;
typedef struct
{
__IO uint32_t LIN_BKFL:4;
__I uint32_t RESERVE0:2;
__IO uint32_t LIN_RX_EN:1;
__IO uint32_t LIN_TX_EN:1;
__IO uint32_t RS485_NMM:1;
__IO uint32_t RS485_AAD:1;
__IO uint32_t RS485_AUD:1;
__I uint32_t RESERVE1:4;
__IO uint32_t RS485_ADD_EN:1;
__I uint32_t RESERVE2:8;
__IO uint32_t ADDR_MATCH:8;
} UART_ALTCON_T;
typedef struct
{
__IO uint32_t FUN_SEL:2;
__I uint32_t RESERVE0:30;
} UART_FUNSEL_T;
typedef struct
{
union {
__IO uint32_t u32DATA;
__IO uint32_t DATA;
};
union {
__IO uint32_t u32IER;
struct {
__IO uint32_t RDA_IEN:1;
__IO uint32_t THRE_IEN:1;
__IO uint32_t RLS_IEN:1;
__IO uint32_t MODEM_IEN:1;
__IO uint32_t RTO_IEN:1;
__IO uint32_t BUF_ERR_IEN:1;
__IO uint32_t WAKE_EN:1;
__I uint32_t RESERVE1:4;
__IO uint32_t TIME_OUT_EN:1;
__IO uint32_t AUTO_RTS_EN:1;
__IO uint32_t AUTO_CTS_EN:1;
__I uint32_t RESERVE2:18;
} IER;
};
union {
__IO uint32_t u32FCR;
struct {
__I uint32_t RESERVE0:1;
__IO uint32_t RFR:1;
__IO uint32_t TFR:1;
__IO uint32_t RESERVE1:1;
__IO uint32_t RFITL:4;
__IO uint32_t RX_DIS:1;
__I uint32_t RESERVE2 :7;
__IO uint32_t RTS_TRI_LEV:4;
__I uint32_t RESERVE3 :4;
} FCR;
};
union {
__IO uint32_t u32LCR;
struct {
__IO uint32_t WLS:2;
__IO uint32_t NSB:1;
__IO uint32_t PBE:1;
__IO uint32_t EPE:1;
__IO uint32_t SPE:1;
__IO uint32_t BCB:1;
__I uint32_t RESERVE :25;
} LCR;
};
union {
__IO uint32_t u32MCR;
struct {
__I uint32_t RESERVE0:1;
__IO uint32_t RTS:1;
__I uint32_t RESERVE1:7;
__IO uint32_t LEV_RTS:1;
__I uint32_t RESERVE2:3;
__IO uint32_t RTS_ST:1;
__I uint32_t RESERVE3:18;
} MCR;
};
union {
__IO uint32_t u32MSR;
struct {
__IO uint32_t DCTSF:1;
__I uint32_t RESERVE0:3;
__IO uint32_t CTS_ST:1;
__I uint32_t RESERVE1:3;
__IO uint32_t LEV_CTS:1;
__I uint32_t RESERVE2:23;
} MSR;
};
union {
__IO uint32_t u32FSR;
struct {
__IO uint32_t RX_OVER_IF:1;
__I uint32_t RESERVE0:2;
__IO uint32_t RS485_ADD_DETF:1;
__IO uint32_t PEF:1;
__IO uint32_t FEF:1;
__IO uint32_t BIF:1;
__I uint32_t RESERVE1:1;
__IO uint32_t RX_POINTER:6;
__IO uint32_t RX_EMPTY:1;
__IO uint32_t RX_FULL:1;
__IO uint32_t TX_POINTER:6;
__IO uint32_t TX_EMPTY:1;
__IO uint32_t TX_FULL:1;
__IO uint32_t TX_OVER_IF:1;
__I uint32_t RESERVE2:3;
__IO uint32_t TE_FLAG:1;
__I uint32_t RESERVE3:3;
} FSR;
};
union {
__IO uint32_t u32ISR;
struct {
__IO uint32_t RDA_IF:1;
__IO uint32_t THRE_IF:1;
__IO uint32_t RLS_IF:1;
__IO uint32_t MODEM_IF:1;
__IO uint32_t TOUT_IF:1;
__IO uint32_t BUF_ERR_IF:1;
__I uint32_t RESERVE0:2;
__IO uint32_t RDA_INT:1;
__IO uint32_t THRE_INT:1;
__IO uint32_t RLS_INT:1;
__IO uint32_t MODEM_INT:1;
__IO uint32_t TOUT_INT:1;
__IO uint32_t BUF_ERR_INT:1;
__I uint32_t RESERVE1:18;
} ISR;
};
union {
__IO uint32_t u32TOR;
struct {
__IO uint32_t TOIC:8;
__IO uint32_t DLY:8;
__I uint32_t RESERVE1:16;
} TOR;
};
union {
__IO uint32_t u32BAUD;
struct {
__IO uint32_t BRD:16;
__I uint32_t RESERVE0:8;
__IO uint32_t DIVIDER_X:4;
__IO uint32_t DIV_X_ONE:1;
__IO uint32_t DIV_X_EN:1;
__I uint32_t RESERVE1:2;
} BAUD;
};
union {
__IO uint32_t u32IRCR;
struct {
__I uint32_t RESERVE0:1;
__IO uint32_t TX_SELECT:1;
__I uint32_t RESERVE1:3;
__IO uint32_t INV_TX:1;
__IO uint32_t INV_RX:1;
__I uint32_t RESERVE2:25;
} IRCR;
};
union {
__IO uint32_t u32ALTCON;
struct {
__I uint32_t RESERVE0:8;
__IO uint32_t RS485_NMM:1;
__IO uint32_t RS485_AAD:1;
__IO uint32_t RS485_AUD:1;
__I uint32_t RESERVE1:4;
__IO uint32_t RS485_ADD_EN :1;
__I uint32_t RESERVE2 :8;
__IO uint32_t ADDR_MATCH :8;
} ALTCON;
};
union {
__IO uint32_t u32FUNSEL;
struct {
__IO uint32_t FUN_SEL:2;
__I uint32_t RESERVE0:30;
} FUNSEL;
};
} UART_T;
/* UART THR Bit Field Definitions */
#define UART_THR_THR_Pos 0
#define UART_THR_THR_Msk (0xFul << UART_THR_THR_Pos)
/* UART RBR Bit Field Definitions */
#define UART_RBR_RBR_Pos 0
#define UART_RBR_RBR_Msk (0xFul << UART_RBR_RBR_Pos)
/* UART IER Bit Field Definitions */
#define UART_IER_AUTO_CTS_EN_Pos 13
#define UART_IER_AUTO_CTS_EN_Msk (1ul << UART_IER_AUTO_CTS_EN_Pos)
#define UART_IER_AUTO_RTS_EN_Pos 12
#define UART_IER_AUTO_RTS_EN_Msk (1ul << UART_IER_AUTO_RTS_EN_Pos)
#define UART_IER_TIME_OUT_EN_Pos 11
#define UART_IER_TIME_OUT_EN_Msk (1ul << UART_IER_TIME_OUT_EN_Pos)
#define UART_IER_WAKE_EN_Pos 6
#define UART_IER_WAKE_EN_Msk (1ul << UART_IER_WAKE_EN_Pos)
#define UART_IER_BUF_ERR_IEN_Pos 5
#define UART_IER_BUF_ERR_IEN_Msk (1ul << UART_IER_BUF_ERR_IEN_Pos)
#define UART_IER_RTO_IEN_Pos 4
#define UART_IER_RTO_IEN_Msk (1ul << UART_IER_RTO_IEN_Pos)
#define UART_IER_MODEM_IEN_Pos 3
#define UART_IER_MODEM_IEN_Msk (1ul << UART_IER_MODEM_IEN_Pos)
#define UART_IER_RLS_IEN_Pos 2
#define UART_IER_RLS_IEN_Msk (1ul << UART_IER_RLS_IENN_Pos)
#define UART_IER_THRE_IEN_Pos 1
#define UART_IER_THRE_IEN_Msk (1ul << UART_IER_THRE_IEN_Pos)
#define UART_IER_RDA_IEN_Pos 0
#define UART_IER_RDA_IEN_Msk (1ul << UART_IER_RDA_IEN_Pos)
/* UART FCR Bit Field Definitions */
#define UART_FCR_RTS_TRI_LEV_Pos 16
#define UART_FCR_RTS_TRI_LEV_Msk (0xFul << UART_FCR_RTS_TRI_LEV_Pos)
#define UART_FCR_RX_DIS_Pos 8
#define UART_FCR_RX_DIS_Msk (1ul << UART_FCR_RX_DIS_Pos)
#define UART_FCR_RFITL_Pos 4
#define UART_FCR_RFITL_Msk (0xFul << UART_FCR_RFITL_Pos)
#define UART_FCR_TFR_Pos 2
#define UART_FCR_TFR_Msk (1ul << UART_FCR_TFR_Pos)
#define UART_FCR_RFR_Pos 1
#define UART_FCR_RFR_Msk (1ul << UART_FCR_RFR_Pos)
/* UART LCR Bit Field Definitions */
#define UART_LCR_BCB_Pos 6
#define UART_LCR_BCB_Msk (1ul << UART_LCR_BCB_Pos)
#define UART_LCR_SPE_Pos 5
#define UART_LCR_SPE_Msk (1ul << UART_LCR_SPE_Pos)
#define UART_LCR_EPE_Pos 4
#define UART_LCR_EPE_Msk (1ul << UART_LCR_EPE_Pos)
#define UART_LCR_PBE_Pos 3
#define UART_LCR_PBE_Msk (1ul << UART_LCR_PBE_Pos)
#define UART_LCR_NSB_Pos 2
#define UART_LCR_NSB_Msk (1ul << UART_LCR_NSB_Pos)
#define UART_LCR_WLS_Pos 0
#define UART_LCR_WLS_Msk (0x3ul << UART_LCR_WLS_Pos)
/* UART MCR Bit Field Definitions */
#define UART_MCR_RTS_ST_Pos 13
#define UART_MCR_RTS_ST_Msk (1ul << UART_MCR_RTS_ST_Pos)
#define UART_MCR_LEV_RTS_Pos 9
#define UART_MCR_LEV_RTS_Msk (1ul << UART_MCR_LEV_RTS_Pos)
#define UART_MCR_RTS_Pos 1
#define UART_MCR_RTS_Msk (1ul << UART_MCR_RTS_Pos)
/* UART MSR Bit Field Definitions */
#define UART_MSR_LEV_CTS_Pos 8
#define UART_MSR_LEV_CTS_Msk (1ul << UART_MSR_LEV_CTS_Pos)
#define UART_MSR_CTS_ST_Pos 4
#define UART_MSR_CTS_ST_Msk (1ul << UART_MSR_CTS_ST_Pos)
#define UART_MSR_DCTSF_Pos 0
#define UART_MSR_DCTSF_Msk (1ul << UART_MSR_DCTSF_Pos)
/* UART FSR Bit Field Definitions */
#define UART_FSR_TE_FLAG_Pos 28
#define UART_FSR_TE_FLAG_Msk (1ul << UART_FSR_TE_FLAG_Pos)
#define UART_FSR_TX_OVER_IF_Pos 24
#define UART_FSR_TX_OVER_IF_Msk (1ul << UART_FSR_TX_OVER_IF_Pos)
#define UART_FSR_TX_FULL_Pos 23
#define UART_FSR_TX_FULL_Msk (1ul << UART_FSR_TX_FULL_Pos)
#define UART_FSR_TX_EMPTY_Pos 22
#define UART_FSR_TX_EMPTY_Msk (1ul << UART_FSR_TX_EMPTY_Pos)
#define UART_FSR_TX_POINTER_Pos 16
#define UART_FSR_TX_POINTER_Msk (0x3Ful << UART_FSR_TX_POINTER_Pos)
#define UART_FSR_RX_FULL_Pos 15
#define UART_FSR_RX_FULL_Msk (1ul << UART_FSR_RX_FULL_Pos)
#define UART_FSR_RX_EMPTY_Pos 14
#define UART_FSR_RX_EMPTY_Msk (1ul << UART_FSR_RX_EMPTY_Pos)
#define UART_FSR_RX_POINTER_Pos 8
#define UART_FSR_RX_POINTER_Msk (0x3Ful << UART_FSR_RX_POINTER_Pos)
#define UART_FSR_BIF_Pos 6
#define UART_FSR_BIF_Msk (1ul << UART_FSR_BIF_Pos)
#define UART_FSR_FEF_Pos 5
#define UART_FSR_FEF_Msk (1ul << UART_FSR_FEF_Pos)
#define UART_FSR_PEF_Pos 4
#define UART_FSR_PEF_Msk (1ul << UART_FSR_PEF_Pos)
#define UART_FSR_RS485_ADD_DETF_Pos 3
#define UART_FSR_RS485_ADD_DETF_Msk (1ul << UART_FSR_RS485_ADD_DETF_Pos)
#define UART_FSR_RX_OVER_IF_Pos 0
#define UART_FSR_RX_OVER_IF_Msk (1ul << UART_FSR_RX_OVER_IF_Pos)
/* UART ISR Bit Field Definitions */
#define UART_ISR_BUF_ERR_INT_Pos 13
#define UART_ISR_BUF_ERR_INT_Msk (1ul << UART_ISR_BUF_ERR_INT_Pos)
#define UART_ISR_TOUT_INT_Pos 12
#define UART_ISR_TOUT_INT_Msk (1ul << UART_ISR_TOUT_INT_Pos)
#define UART_ISR_MODEM_INT_Pos 11
#define UART_ISR_MODEM_INT_Msk (1ul << UART_ISR_MODEM_INT_Pos)
#define UART_ISR_RLS_INT_Pos 10
#define UART_ISR_RLS_INT_Msk (1ul << UART_ISR_RLS_INT_Pos)
#define UART_ISR_THRE_INT_Pos 9
#define UART_ISR_THRE_INT_Msk (1ul << UART_ISR_THRE_INT_Pos)
#define UART_ISR_RDA_INT_Pos 8
#define UART_ISR_RDA_INT_Msk (1ul << UART_ISR_RDA_INT_Pos)
#define UART_ISR_BUF_ERR_IF_Pos 5
#define UART_ISR_BUF_ERR_IF_Msk (1ul << UART_ISR_BUF_ERR_IF_Pos)
#define UART_ISR_TOUT_IF_Pos 4
#define UART_ISR_TOUT_IF_Msk (1ul << UART_ISR_TOUT_IF_Pos)
#define UART_ISR_MODEM_IF_Pos 3
#define UART_ISR_MODEM_IF_Msk (1ul << UART_ISR_MODEM_IF_Pos)
#define UART_ISR_RLS_IF_Pos 2
#define UART_ISR_RLS_IF_Msk (1ul << UART_ISR_RLS_IF_Pos)
#define UART_ISR_THRE_IF_Pos 1
#define UART_ISR_THRE_IF_Msk (1ul << UART_ISR_THRE_IF_Pos)
#define UART_ISR_RDA_IF_Pos 0
#define UART_ISR_RDA_IF_Msk (1ul << UART_ISR_RDA_IF_Pos)
/* UART TOR Bit Field Definitions */
#define UART_TOR_DLY_Pos 8
#define UART_TOR_DLY_Msk (0xFFul << UART_TOR_DLY_Pos)
#define UART_TOR_TOIC_Pos 0
#define UART_TOR_TOIC_Msk (0xFFul << UART_TOR_TOIC_Pos)
/* UART BAUD Bit Field Definitions */
#define UART_BAUD_DIV_X_EN_Pos 29
#define UART_BAUD_DIV_X_EN_Msk (1ul << UART_BAUD_DIV_X_EN_Pos)
#define UART_BAUD_DIV_X_ONE_Pos 28
#define UART_BAUD_DIV_X_ONE_Msk (1ul << UART_BAUD_DIV_X_ONE_Pos)
#define UART_BAUD_DIVIDER_X_Pos 24
#define UART_BAUD_DIVIDER_X_Msk (0xFul << UART_BAUD_DIVIDER_X_Pos)
#define UART_BAUD_BRD_Pos 0
#define UART_BAUD_BRD_Msk (0xFFul << UART_BAUD_BRD_Pos)
/* UART IRCR Bit Field Definitions */
#define UART_IRCR_INV_RX_Pos 6
#define UART_IRCR_INV_RX_Msk (1ul << UART_IRCR_INV_RX_Pos)
#define UART_IRCR_INV_TX_Pos 5
#define UART_IRCR_INV_TX_Msk (1ul << UART_IRCR_INV_TX_Pos)
#define UART_IRCR_TX_SELECT_Pos 1
#define UART_IRCR_TX_SELECT_Msk (1ul << UART_IRCR_TX_SELECT_Pos)
/* UART ALT_CSR Bit Field Definitions */
#define UART_ALT_CSR_ADDR_MATCH_Pos 24
#define UART_ALT_CSR_ADDR_MATCH_Msk (0xFFul << UART_ALT_CSR_ADDR_MATCH_Pos)
#define UART_ALT_CSR_RS485_ADD_EN_Pos 15
#define UART_ALT_CSR_RS485_ADD_EN_Msk (1ul << UART_ALT_CSR_RS485_ADD_EN_Pos)
#define UART_ALT_CSR_RS485_AUD_Pos 10
#define UART_ALT_CSR_RS485_AUD_Msk (1ul << UART_ALT_CSR_RS485_AUD_Pos)
#define UART_ALT_CSR_RS485_AAD_Pos 9
#define UART_ALT_CSR_RS485_AAD_Msk (1ul << UART_ALT_CSR_RS485_AAD_Pos)
#define UART_ALT_CSR_RS485_NMM_Pos 8
#define UART_ALT_CSR_RS485_NMM_Msk (1ul << UART_ALT_CSR_RS485_NMM_Pos)
/* UART FUN_SEL Bit Field Definitions */
#define UART_FUN_SEL_FUN_SEL_Pos 0
#define UART_FUN_SEL_FUN_SEL_Msk (0x3ul << UART_FUN_SEL_FUN_SEL_Pos)
/*----------------------------- Timer Controller -----------------------------*/
typedef struct
{
__IO uint32_t PRESCALE:8;
__I uint32_t RESERVE0:8;
__IO uint32_t TDR_EN:1;
__I uint32_t RESERVE1:7;
__IO uint32_t CTB:1;
__IO uint32_t CACT:1;
__IO uint32_t CRST:1;
__IO uint32_t MODE:2;
__IO uint32_t IE:1;
__IO uint32_t CEN:1;
__IO uint32_t DBGACK_TMR:1;
} TIMER_TCSR_T;
typedef __IO uint32_t TIMER_TCMPR_T;
typedef struct
{
__IO uint32_t TIF:1;
__I uint32_t RESERVE:31;
} TIMER_TISR_T;
typedef __IO uint32_t TIMER_TDR_T;
typedef struct
{
union {
__IO uint32_t u32TCSR;
struct {
__IO uint32_t PRESCALE:8;
__I uint32_t RESERVE0:8;
__IO uint32_t TDR_EN:1;
__I uint32_t RESERVE1:7;
__IO uint32_t CTB:1;
__IO uint32_t CACT:1;
__IO uint32_t CRST:1;
__IO uint32_t MODE:2;
__IO uint32_t IE:1;
__IO uint32_t CEN:1;
__IO uint32_t DBGACK_TMR:1;
} TCSR;
};
union {
__IO uint32_t u32TCMPR;
__IO uint32_t TCMPR;
};
union {
__IO uint32_t u32TISR;
struct {
__IO uint32_t TIF:1;
__I uint32_t RESERVE:31;
} TISR;
};
union {
__IO uint32_t u32TDR;
__IO uint32_t TDR;
};
} TIMER_T;
/* Timer TCSR Bit Field Definitions */
#define TIMER_TCSR_DBGACK_TMR_Pos 31
#define TIMER_TCSR_DBGACK_TMR_Msk (1ul << TIMER_TCSR_DBGACK_TMR_Pos)
#define TIMER_TCSR_CEN_Pos 30
#define TIMER_TCSR_CEN_Msk (1ul << TIMER_TCSR_CEN_Pos)
#define TIMER_TCSR_IE_Pos 29
#define TIMER_TCSR_IE_Msk (1ul << TIMER_TCSR_IE_Pos)
#define TIMER_TCSR_MODE_Pos 27
#define TIMER_TCSR_MODE_Msk (0x3ul << TIMER_TCSR_MODE_Pos)
#define TIMER_TCSR_CRST_Pos 26
#define TIMER_TCSR_CRST_Msk (1ul << TIMER_TCSR_CRST_Pos)
#define TIMER_TCSR_CACT_Pos 25
#define TIMER_TCSR_CACT_Msk (1ul << TIMER_TCSR_CACT_Pos)
#define TIMER_TCSR_CTB_Pos 24
#define TIMER_TCSR_CTB_Msk (1ul << TIMER_TCSR_CTB_Pos)
#define TIMER_TCSR_TDR_EN_Pos 16
#define TIMER_TCSR_TDR_EN_Msk (1ul << TIMER_TCSR_TDR_EN_Pos)
#define TIMER_TCSR_PRESCALE_Pos 0
#define TIMER_TCSR_PRESCALE_Msk (0xFFul << TIMER_TCSR_PRESCALE_Pos)
/* Timer TCMPR Bit Field Definitions */
#define TIMER_TCMP_Pos 0
#define TIMER_TCMP_Msk (0xFFFFFFul << TIMER_TCMP_Pos)
/* Timer TISR Bit Field Definitions */
#define TIMER_TISR_TIF_Pos 0
#define TIMER_TISR_TIF_Msk (1ul << TIMER_TISR_TIF_Pos)
/* Timer TDR Bit Field Definitions */
#define TIMER_TDR_Pos 0
#define TIMER_TDR_Msk (0xFFFFFFul << TIMER_TDR_Pos)
/*----------------------------- WDT Controller -----------------------------*/
typedef struct
{
__IO uint32_t WTR:1;
__IO uint32_t WTRE:1;
__IO uint32_t WTRF:1;
__IO uint32_t WTIF:1;
__IO uint32_t WTWKE:1;
__IO uint32_t WTWKF:1;
__IO uint32_t WTIE:1;
__IO uint32_t WTE:1;
__IO uint32_t WTIS:3;
__I uint32_t RESERVE1:20;
__IO uint32_t DBGACK_WDT:1;
} WDT_WTCR_T;
typedef struct
{
union {
__IO uint32_t u32WTCR;
struct {
__IO uint32_t WTR:1;
__IO uint32_t WTRE:1;
__IO uint32_t WTRF:1;
__IO uint32_t WTIF:1;
__IO uint32_t WTWKE:1;
__IO uint32_t WTWKF:1;
__IO uint32_t WTIE:1;
__IO uint32_t WTE:1;
__IO uint32_t WTIS:3;
__I uint32_t RESERVE1:20;
__IO uint32_t DBGACK_WDT:1;
} WTCR;
};
} WDT_T;
/* WDT WTCR Bit Field Definitions */
#define WDT_WTCR_DBGACK_WDT_Pos 31
#define WDT_WTCR_DBGACK_WDT_Msk (1ul << WDT_WTCR_DBGACK_WDT_Pos)
#define WDT_WTCR_WTIS_Pos 8
#define WDT_WTCR_WTIS_Msk (0x3ul << WDT_WTCR_WTIS_Pos)
#define WDT_WTCR_WTE_Pos 7
#define WDT_WTCR_WTE_Msk (1ul << WDT_WTCR_WTE_Pos)
#define WDT_WTCR_WTIE_Pos 6
#define WDT_WTCR_WTIE_Msk (1ul << WDT_WTCR_WTIE_Pos)
#define WDT_WTCR_WTWKF_Pos 5
#define WDT_WTCR_WTWKF_Msk (1ul << WDT_WTCR_WTWKF_Pos)
#define WDT_WTCR_WTWKE_Pos 4
#define WDT_WTCR_WTWKE_Msk (1ul << WDT_WTCR_WTWKE_Pos)
#define WDT_WTCR_WTIF_Pos 3
#define WDT_WTCR_WTIF_Msk (1ul << WDT_WTCR_WTIF_Pos)
#define WDT_WTCR_WTRF_Pos 2
#define WDT_WTCR_WTRF_Msk (1ul << WDT_WTCR_WTRF_Pos)
#define WDT_WTCR_WTRE_Pos 1
#define WDT_WTCR_WTRE_Msk (1ul << WDT_WTCR_WTRE_Pos)
#define WDT_WTCR_WTR_Pos 0
#define WDT_WTCR_WTR_Msk (1ul << WDT_WTCR_WTR_Pos)
/*------------------------- SPI Interface Controller -------------------------*/
typedef struct
{
__IO uint32_t GO_BUSY:1;
__IO uint32_t RX_NEG:1;
__IO uint32_t TX_NEG:1;
__IO uint32_t TX_BIT_LEN:5;
__IO uint32_t TX_NUM:2;
__IO uint32_t LSB:1;
__IO uint32_t CLKP:1;
__IO uint32_t SP_CYCLE:4;
__IO uint32_t IF:1;
__IO uint32_t IE:1;
__IO uint32_t SLAVE:1;
__IO uint32_t REORDER:2;
__IO uint32_t FIFO:1;
__I uint32_t RESERVE0:1;
__IO uint32_t VARCLK_EN:1;
__I uint32_t RX_EMPTY:1;
__I uint32_t RX_FULL:1;
__I uint32_t TX_EMPTY:1;
__I uint32_t TX_FULL:1;
__I uint32_t RESERVE1:4;
} SPI_CNTRL_T;
typedef struct
{
__IO uint32_t DIVIDER:16;
__IO uint32_t DIVIDER2:16;
} SPI_DIVIDER_T;
typedef struct
{
__IO uint32_t SSR:2;
__IO uint32_t SS_LVL:1;
__IO uint32_t AUTOSS:1;
__IO uint32_t SS_LTRIG:1;
__I uint32_t LTRIG_FLAG:1;
__I uint32_t RESERVE:26;
} SPI_SSR_T;
typedef __I uint32_t SPI_RX_T;
typedef __O uint32_t SPI_TX_T;
typedef __IO uint32_t SPI_VARCLK_T;
typedef struct
{
union {
__IO uint32_t u32CNTRL;
struct {
__IO uint32_t GO_BUSY:1;
__IO uint32_t RX_NEG:1;
__IO uint32_t TX_NEG:1;
__IO uint32_t TX_BIT_LEN:5;
__IO uint32_t TX_NUM:2;
__IO uint32_t LSB:1;
__IO uint32_t CLKP:1;
__IO uint32_t SP_CYCLE:4;
__IO uint32_t IF:1;
__IO uint32_t IE:1;
__IO uint32_t SLAVE:1;
__IO uint32_t REORDER:2;
__IO uint32_t FIFO:1;
__I uint32_t RESERVE0:1;
__IO uint32_t VARCLK_EN:1;
__I uint32_t RX_EMPTY:1;
__I uint32_t RX_FULL:1;
__I uint32_t TX_EMPTY:1;
__I uint32_t TX_FULL:1;
__I uint32_t RESERVE1:4;
} CNTRL;
};
union {
__IO uint32_t u32DIVIDER;
struct {
__IO uint32_t DIVIDER:16;
__IO uint32_t DIVIDER2:16;
} DIVIDER;
};
union {
__IO uint32_t u32SSR;
struct {
__IO uint32_t SSR:2;
__IO uint32_t SS_LVL:1;
__IO uint32_t AUTOSS:1;
__IO uint32_t SS_LTRIG:1;
__I uint32_t LTRIG_FLAG:1;
__I uint32_t RESERVE:26;
} SSR;
};
__I uint32_t RESERVE0;
union {
__I uint32_t u32RX[2];
__I uint32_t RX[2];
};
__I uint32_t RESERVE1;
__I uint32_t RESERVE2;
union {
__O uint32_t u32TX[2];
__O uint32_t TX[2];
};
__I uint32_t RESERVE3;
__I uint32_t RESERVE4;
__I uint32_t RESERVE5;
union {
__IO uint32_t u32VARCLK;
__IO uint32_t VARCLK;
};
} SPI_T;
/* SPI_CNTRL Bit Field Definitions */
#define SPI_CNTRL_TX_FULL_Pos 27
#define SPI_CNTRL_TX_FULL_Msk (1ul << SPI_CNTRL_TX_FULL_Pos)
#define SPI_CNTRL_TX_EMPTY_Pos 26
#define SPI_CNTRL_TX_EMPTY_Msk (1ul << SPI_CNTRL_TX_EMPTY_Pos)
#define SPI_CNTRL_RX_FULL_Pos 25
#define SPI_CNTRL_RX_FULL_Msk (1ul << SPI_CNTRL_RX_FULL_Pos)
#define SPI_CNTRL_RX_EMPTY_Pos 24
#define SPI_CNTRL_RX_EMPTY_Msk (1ul << SPI_CNTRL_RX_EMPTY_Pos)
#define SPI_CNTRL_VARCLK_EN_Pos 23
#define SPI_CNTRL_VARCLK_EN_Msk (1ul << SPI_CNTRL_VARCLK_EN_Pos)
#define SPI_CNTRL_FIFO_Pos 21
#define SPI_CNTRL_FIFO_Msk (1ul << SPI_CNTRL_FIFO_Pos)
#define SPI_CNTRL_REORDER_Pos 19
#define SPI_CNTRL_REORDER_Msk (3ul << SPI_CNTRL_REORDER_Pos)
#define SPI_CNTRL_SLAVE_Pos 18
#define SPI_CNTRL_SLAVE_Msk (1ul << SPI_CNTRL_SLAVE_Pos)
#define SPI_CNTRL_IE_Pos 17
#define SPI_CNTRL_IE_Msk (1ul << SPI_CNTRL_IE_Pos)
#define SPI_CNTRL_IF_Pos 16
#define SPI_CNTRL_IF_Msk (1ul << SPI_CNTRL_IF_Pos)
#define SPI_CNTRL_SP_CYCLE_Pos 12
#define SPI_CNTRL_SP_CYCLE_Msk (0xFul << SPI_CNTRL_SP_CYCLE_Pos)
#define SPI_CNTRL_CLKP_Pos 11
#define SPI_CNTRL_CLKP_Msk (1ul << SPI_CNTRL_CLKP_Pos)
#define SPI_CNTRL_LSB_Pos 10
#define SPI_CNTRL_LSB_Msk (1ul << SPI_CNTRL_LSB_Pos)
#define SPI_CNTRL_TX_NUM_Pos 8
#define SPI_CNTRL_TX_NUM_Msk (3ul << SPI_CNTRL_TX_NUM_Pos)
#define SPI_CNTRL_TX_BIT_LEN_Pos 3
#define SPI_CNTRL_TX_BIT_LEN_Msk (0x1Ful << SPI_CNTRL_TX_BIT_LEN_Pos)
#define SPI_CNTRL_TX_NEG_Pos 2
#define SPI_CNTRL_TX_NEG_Msk (1ul << SPI_CNTRL_TX_NEG_Pos)
#define SPI_CNTRL_RX_NEG_Pos 1
#define SPI_CNTRL_RX_NEG_Msk (1ul << SPI_CNTRL_RX_NEG_Pos)
#define SPI_CNTRL_GO_BUSY_Pos 0
#define SPI_CNTRL_GO_BUSY_Msk (1ul << SPI_CNTRL_GO_BUSY_Pos)
/* SPI_DIVIDER Bit Field Definitions */
#define SPI_DIVIDER_DIVIDER2_Pos 16
#define SPI_DIVIDER_DIVIDER2_Msk (0xFFFFul << SPI_DIVIDER_DIVIDER2_Pos)
#define SPI_DIVIDER_DIVIDER_Pos 0
#define SPI_DIVIDER_DIVIDER_Msk (0xFFFFul << SPI_DIVIDER_DIVIDER_Pos)
/* SPI_SSR Bit Field Definitions */
#define SPI_SSR_LTRIG_FLAG_Pos 5
#define SPI_SSR_LTRIG_FLAG_Msk (1ul << SPI_SSR_LTRIG_FLAG_Pos)
#define SPI_SSR_SS_LTRIG_Pos 4
#define SPI_SSR_SS_LTRIG_Msk (1ul << SPI_SSR_SS_LTRIG_Pos)
#define SPI_SSR_AUTOSS_Pos 3
#define SPI_SSR_AUTOSS_Msk (1ul << SPI_SSR_AUTOSS_Pos)
#define SPI_SSR_SS_LVL_Pos 2
#define SPI_SSR_SS_LVL_Msk (1ul << SPI_SSR_SS_LVL_Pos)
#define SPI_SSR_SSR_Pos 0
#define SPI_SSR_SSR_Msk (3ul << SPI_SSR_SSR_Pos)
/*------------------------------ I2C Controller ------------------------------*/
typedef struct
{
__I uint32_t RESERVE0:2;
__IO uint32_t AA:1;
__IO uint32_t SI:1;
__IO uint32_t STO:1;
__IO uint32_t STA:1;
__IO uint32_t ENS1:1;
__IO uint32_t EI:1;
__I uint32_t RESERVE1:24;
} I2C_I2CON_T;
typedef struct
{
__IO uint32_t GC:1;
__IO uint32_t I2CADDR:7;
__I uint32_t RESERVE:24;
} I2C_I2CADDR_T;
typedef __IO uint32_t I2C_I2CDAT_T;
typedef __I uint32_t I2C_I2CSTATUS_T;
typedef __IO uint32_t I2C_I2CLK_T;
typedef struct
{
__IO uint32_t TIF:1;
__IO uint32_t DIV4:1;
__IO uint32_t ENTI:1;
__I uint32_t RESERVE:29;
} I2C_I2CTOC_T;
typedef struct
{
__I uint32_t RESERVE0:1;
__IO uint32_t I2CADM:7;
__I uint32_t RESERVE1:24;
} I2C_I2CADM_T;
typedef struct
{
union
{
__IO uint32_t u32I2CON;
struct
{
__I uint32_t RESERVE0:2;
__IO uint32_t AA:1;
__IO uint32_t SI:1;
__IO uint32_t STO:1;
__IO uint32_t STA:1;
__IO uint32_t ENS1:1;
__IO uint32_t EI:1;
__I uint32_t RESERVE1:24;
} I2CON;
};
union
{
__IO uint32_t u32I2CADDR0;
struct
{
__IO uint32_t GC:1;
__IO uint32_t I2CADDR:7;
__I uint32_t RESERVE:24;
} I2CADDR0;
};
union
{
__IO uint32_t u32I2CDAT;
__IO uint32_t I2CDAT;
};
union
{
__I uint32_t u32I2CSTATUS;
__I uint32_t I2CSTATUS;
};
union
{
__IO uint32_t u32I2CLK;
__IO uint32_t I2CLK;
};
union
{
__IO uint32_t u32I2CTOC;
struct
{
__IO uint32_t TIF:1;
__IO uint32_t DIV4:1;
__IO uint32_t ENTI:1;
__I uint32_t RESERVE:29;
} I2CTOC;
};
union
{
__IO uint32_t u32I2CADDR1;
struct
{
__IO uint32_t GC:1;
__IO uint32_t I2CADDR:7;
__I uint32_t RESERVE:24;
} I2CADDR1;
};
union
{
__IO uint32_t u32I2CADDR2;
struct
{
__IO uint32_t GC:1;
__IO uint32_t I2CADDR:7;
__I uint32_t RESERVE:24;
} I2CADDR2;
};
union
{
__IO uint32_t u32I2CADDR3;
struct
{
__IO uint32_t GC:1;
__IO uint32_t I2CADDR:7;
__I uint32_t RESERVE:24;
} I2CADDR3;
};
union
{
__IO uint32_t u32I2CADM0;
struct
{
__I uint32_t RESERVE0:1;
__IO uint32_t I2CADM:7;
__I uint32_t RESERVE1:24;
} I2CADM0;
};
union
{
__IO uint32_t u32I2CADM1;
struct
{
__I uint32_t RESERVE0:1;
__IO uint32_t I2CADM:7;
__I uint32_t RESERVE1:24;
} I2CADM1;
};
union
{
__IO uint32_t u32I2CADM2;
struct
{
__I uint32_t RESERVE0:1;
__IO uint32_t I2CADM:7;
__I uint32_t RESERVE1:24;
} I2CADM2;
};
union
{
__IO uint32_t u32I2CADM3;
struct
{
__I uint32_t RESERVE0:1;
__IO uint32_t I2CADM:7;
__I uint32_t RESERVE1:24;
} I2CADM3;
};
} I2C_T;
/* I2C I2CON Bit Field Definitions */
#define I2C_I2CON_EI_Pos 7
#define I2C_I2CON_EI_Msk (1ul << I2C_I2CON_EI_Pos)
#define I2C_I2CON_ENS1_Pos 6
#define I2C_I2CON_ENS1_Msk (1ul << I2C_I2CON_ENS1_Pos)
#define I2C_I2CON_STA_Pos 5
#define I2C_I2CON_STA_Msk (1ul << I2C_I2CON_STA_Pos)
#define I2C_I2CON_STO_Pos 4
#define I2C_I2CON_STO_Msk (1ul << I2C_I2CON_STO_Pos)
#define I2C_I2CON_SI_Pos 3
#define I2C_I2CON_SI_Msk (1ul << I2C_I2CON_SI_Pos)
#define I2C_I2CON_AA_Pos 2
#define I2C_I2CON_AA_Msk (1ul << I2C_I2CON_AA_Pos)
/* I2C I2CADDR Bit Field Definitions */
#define I2C_I2CADDR_I2CADDR_Pos 1
#define I2C_I2CADDR_I2CADDR_Msk (0x7Ful << I2C_I2CADDR_I2CADDR_Pos)
#define I2C_I2CADDR_GC_Pos 0
#define I2C_I2CADDR_GC_Msk (1ul << I2C_I2CADDR_GC_Pos)
/* I2C I2CDAT Bit Field Definitions */
#define I2C_I2CDAT_I2CDAT_Pos 0
#define I2C_I2CDAT_I2CDAT_Msk (0xFFul << I2C_I2CDAT_I2CDAT_Pos)
/* I2C I2CSTATUS Bit Field Definitions */
#define I2C_I2CSTATUS_I2CSTATUS_Pos 0
#define I2C_I2CSTATUS_I2CSTATUS_Msk (0xFFul << I2C_I2CSTATUS_I2CSTATUS_Pos)
/* I2C I2CLK Bit Field Definitions */
#define I2C_I2CLK_I2CLK_Pos 0
#define I2C_I2CLK_I2CLK_Msk (0xFFul << I2C_I2CLK_I2CLK_Pos)
/* I2C I2CTOC Bit Field Definitions */
#define I2C_I2CTOC_ENTI_Pos 2
#define I2C_I2CTOC_ENTI_Msk (1ul << I2C_I2CTOC_ENTI_Pos)
#define I2C_I2CTOC_DIV4_Pos 1
#define I2C_I2CTOC_DIV4_Msk (1ul << I2C_I2CTOC_DIV4_Pos)
#define I2C_I2CTOC_TIF_Pos 0
#define I2C_I2CTOC_TIF_Msk (1ul << I2C_I2CTOC_TIF_Pos)
/* I2C I2CADM Bit Field Definitions */
#define I2C_I2CADM_I2CADM_Pos 1
#define I2C_I2CADM_I2CADM_Msk (0x7Ful << I2C_I2CADM_I2CADM_Pos)
/*----------------------------- RTC Controller -------------------------------*/
typedef __IO uint32_t RTC_INIR_T;
typedef struct
{
__IO uint32_t AER:16;
__I uint32_t ENF:1;
__I uint32_t RESERVE1:15;
} RTC_AER_T;
typedef struct
{
__IO uint32_t FRACTION:6;
__I uint32_t RESERVE0:2;
__IO uint32_t INTEGER:4;
__I uint32_t RESERVE1:20;
} RTC_FCR_T;
typedef struct
{
__IO uint32_t SEC1:4;
__IO uint32_t SEC10:3;
__I uint32_t RESERVE0:1;
__IO uint32_t MIN1:4;
__IO uint32_t MIN10:3;
__I uint32_t RESERVE1:1;
__IO uint32_t HR1:4;
__IO uint32_t HR10:2;
__I uint32_t RESERVE2:10;
} RTC_TLR_T;
typedef struct
{
__IO uint32_t DAY1:4;
__IO uint32_t DAY10:2;
__I uint32_t RESERVE0:2;
__IO uint32_t MON1:4;
__IO uint32_t MON10:1;
__I uint32_t RESERVE1:3;
__IO uint32_t YEAR1:4;
__IO uint32_t YEAR10:4;
__I uint32_t RESERVE2:8;
} RTC_CLR_T;
typedef struct
{
__IO uint32_t HR24_HR12:1;
__I uint32_t RESERVE:31;
} RTC_TSSR_T;
typedef struct
{
__IO uint32_t DWR:3;
__I uint32_t RESERVE:29;
} RTC_DWR_T;
typedef RTC_TLR_T RTC_TAR_T;
typedef RTC_CLR_T RTC_CAR_T;
typedef struct
{
__IO uint32_t LIR:1;
__I uint32_t RESERVE:31;
} RTC_LIR_T;
typedef struct
{
__IO uint32_t AIER:1;
__IO uint32_t TIER:1;
__I uint32_t RESERVE:30;
} RTC_RIER_T;
typedef struct
{
__IO uint32_t AIF:1;
__IO uint32_t TIF:1;
__I uint32_t RESERVE:30;
} RTC_RIIR_T;
typedef struct
{
__IO uint32_t TTR:3;
__IO uint32_t TWKE:1;
__I uint32_t RESERVE:28;
} RTC_TTR_T;
typedef struct
{
union {
__IO uint32_t u32INIR;
__IO uint32_t INIR;
};
union {
__IO uint32_t u32AER;
struct {
__IO uint32_t AER:16;
__I uint32_t ENF:1;
__I uint32_t RESERVE1:15;
} AER;
};
union {
__IO uint32_t u32FCR;
struct {
__IO uint32_t FRACTION:6;
__I uint32_t RESERVE0:2;
__IO uint32_t INTEGER:4;
__I uint32_t RESERVE1:20;
} FCR;
};
union {
__IO uint32_t u32TLR;
struct {
__IO uint32_t SEC1:4;
__IO uint32_t SEC10:3;
__I uint32_t RESERVE0:1;
__IO uint32_t MIN1:4;
__IO uint32_t MIN10:3;
__I uint32_t RESERVE1:1;
__IO uint32_t HR1:4;
__IO uint32_t HR10:2;
__I uint32_t RESERVE2:10;
} TLR;
};
union {
__IO uint32_t u32CLR;
struct {
__IO uint32_t DAY1:4;
__IO uint32_t DAY10:2;
__I uint32_t RESERVE0:2;
__IO uint32_t MON1:4;
__IO uint32_t MON10:1;
__I uint32_t RESERVE1:3;
__IO uint32_t YEAR1:4;
__IO uint32_t YEAR10:4;
__I uint32_t RESERVE2:8;
} CLR;
};
union {
__IO uint32_t u32TSSR;
struct {
__IO uint32_t HR24_HR12:1;
__I uint32_t RESERVE:31;
} TSSR;
};
union {
__IO uint32_t u32DWR;
struct {
__IO uint32_t DWR:3;
__I uint32_t RESERVE:29;
} DWR;
};
union {
__IO uint32_t u32TAR;
struct {
__IO uint32_t SEC1:4;
__IO uint32_t SEC10:3;
__I uint32_t RESERVE0:1;
__IO uint32_t MIN1:4;
__IO uint32_t MIN10:3;
__I uint32_t RESERVE1:1;
__IO uint32_t HR1:4;
__IO uint32_t HR10:2;
__I uint32_t RESERVE2:10;
} TAR;
};
union {
__IO uint32_t u32CAR;
struct {
__IO uint32_t DAY1:4;
__IO uint32_t DAY10:2;
__I uint32_t RESERVE0:2;
__IO uint32_t MON1:4;
__IO uint32_t MON10:1;
__I uint32_t RESERVE1:3;
__IO uint32_t YEAR1:4;
__IO uint32_t YEAR10:4;
__I uint32_t RESERVE2:8;
} CAR;
};
union {
__IO uint32_t u32LIR;
struct {
__IO uint32_t LIR:1;
__I uint32_t RESERVE:31;
} LIR;
};
union {
__IO uint32_t u32RIER;
struct {
__IO uint32_t AIER:1;
__IO uint32_t TIER:1;
__I uint32_t RESERVE:30;
} RIER;
};
union {
__IO uint32_t u32RIIR;
struct {
__IO uint32_t AIF:1;
__IO uint32_t TIF:1;
__I uint32_t RESERVE:30;
} RIIR;
};
union {
__IO uint32_t u32TTR;
struct {
__IO uint32_t TTR:3;
__IO uint32_t TWKE:1;
__I uint32_t RESERVE:28;
} TTR;
};
} RTC_T;
/* RTC INIR Bit Field Definitions */
#define RTC_INIR_INIR_Pos 0
#define RTC_INIR_INIR_Msk (0xFFFFFFFFul << RTC_INIR_INIR_Pos)
#define RTC_INIR_ACTIVE_Pos 0
#define RTC_INIR_ACTIVE_Msk (1ul << RTC_INIR_ACTIVE_Pos)
/* RTC AER Bit Field Definitions */
#define RTC_AER_ENF_Pos 16
#define RTC_AER_ENF_Msk (1ul << RTC_AER_ENF_Pos)
#define RTC_AER_AER_Pos 0
#define RTC_AER_AER_Msk (0xFFFFul << RTC_AER_AER_Pos)
/* RTC FCR Bit Field Definitions */
#define RTC_FCR_INTEGER_Pos 8
#define RTC_FCR_INTEGER_Msk (0xFul << RTC_FCR_INTEGER_Pos)
#define RTC_FCR_FRACTION_Pos 0
#define RTC_FCR_FRACTION_Msk (0x3Ful << RTC_FCR_FRACTION_Pos)
/* RTC TLR Bit Field Definitions */
#define RTC_TLR_10HR_Pos 20
#define RTC_TLR_10HR_Msk (0x3ul << RTC_TLR_10HR_Pos)
#define RTC_TLR_1HR_Pos 16
#define RTC_TLR_1HR_Msk (0xFul << RTC_TLR_1HR_Pos)
#define RTC_TLR_10MIN_Pos 12
#define RTC_TLR_10MIN_Msk (0x7ul << RTC_TLR_10MIN_Pos)
#define RTC_TLR_1MIN_Pos 8
#define RTC_TLR_1MIN_Msk (0xFul << RTC_TLR_1MIN_Pos)
#define RTC_TLR_10SEC_Pos 4
#define RTC_TLR_10SEC_Msk (0x7ul << RTC_TLR_10SEC_Pos)
#define RTC_TLR_1SEC_Pos 0
#define RTC_TLR_1SEC_Msk (0xFul << RTC_TLR_1SEC_Pos)
/* RTC CLR Bit Field Definitions */
#define RTC_CLR_10YEAR_Pos 20
#define RTC_CLR_10YEAR_Msk (0xFul << RTC_CLR_10YEAR_Pos)
#define RTC_CLR_1YEAR_Pos 16
#define RTC_CLR_1YEAR_Msk (0xFul << RTC_CLR_1YEAR_Pos)
#define RTC_CLR_10MON_Pos 12
#define RTC_CLR_10MON_Msk (1ul << RTC_CLR_10MON_Pos)
#define RTC_CLR_1MON_Pos 8
#define RTC_CLR_1MON_Msk (0xFul << RTC_CLR_1MON_Pos)
#define RTC_CLR_10DAY_Pos 4
#define RTC_CLR_10DAY_Msk (0x3ul << RTC_CLR_10DAY_Pos)
#define RTC_CLR_1DAY_Pos 0
#define RTC_CLR_1DAY_Msk (0xFul << RTC_CLR_1DAY_Pos)
/* RTC TSSR Bit Field Definitions */
#define RTC_TSSR_24H_12H_Pos 0
#define RTC_TSSR_24H_12H_Msk (1ul << RTC_TSSR_24H_12H_Pos)
/* RTC DWR Bit Field Definitions */
#define RTC_DWR_DWR_Pos 0
#define RTC_DWR_DWR_Msk (0x7ul << RTC_DWR_DWR_Pos)
/* RTC TAR Bit Field Definitions */
#define RTC_TAR_10HR_Pos 20
#define RTC_TAR_10HR_Msk (0x3ul << RTC_TAR_10HR_Pos)
#define RTC_TAR_1HR_Pos 16
#define RTC_TAR_1HR_Msk (0xFul << RTC_TAR_1HR_Pos)
#define RTC_TAR_10MIN_Pos 12
#define RTC_TAR_10MIN_Msk (0x7ul << RTC_TAR_10MIN_Pos)
#define RTC_TAR_1MIN_Pos 8
#define RTC_TAR_1MIN_Msk (0xFul << RTC_TAR_1MIN_Pos)
#define RTC_TAR_10SEC_Pos 4
#define RTC_TAR_10SEC_Msk (0x7ul << RTC_TAR_10SEC_Pos)
#define RTC_TAR_1SEC_Pos 0
#define RTC_TAR_1SEC_Msk (0xFul << RTC_TAR_1SEC_Pos)
/* RTC CAR Bit Field Definitions */
#define RTC_CAR_10YEAR_Pos 20
#define RTC_CAR_10YEAR_Msk (0xFul << RTC_CAR_10YEAR_Pos)
#define RTC_CAR_1YEAR_Pos 16
#define RTC_CAR_1YEAR_Msk (0xFul << RTC_CAR_1YEAR_Pos)
#define RTC_CAR_10MON_Pos 12
#define RTC_CAR_10MON_Msk (1ul << RTC_CAR_10MON_Pos)
#define RTC_CAR_1MON_Pos 8
#define RTC_CAR_1MON_Msk (0xFul << RTC_CAR_1MON_Pos)
#define RTC_CAR_10DAY_Pos 4
#define RTC_CAR_10DAY_Msk (0x3ul << RTC_CAR_10DAY_Pos)
#define RTC_CAR_1DAY_Pos 0
#define RTC_CAR_1DAY_Msk (0xFul << RTC_CAR_1DAY_Pos)
/* RTC LIR Bit Field Definitions */
#define RTC_LIR_LIR_Pos 0
#define RTC_LIR_LIR_Msk (1ul << RTC_LIR_LIR_Pos)
/* RTC RIER Bit Field Definitions */
#define RTC_RIER_TIER_Pos 1
#define RTC_RIER_TIER_Msk (1ul << RTC_RIER_TIER_Pos)
#define RTC_RIER_AIER_Pos 0
#define RTC_RIER_AIER_Msk (1ul << RTC_RIER_AIER_Pos)
/* RTC RIIR Bit Field Definitions */
#define RTC_RIIR_TIF_Pos 1
#define RTC_RIIR_TIF_Msk (1ul << RTC_RIIR_TIF_Pos)
#define RTC_RIIR_AIF_Pos 0
#define RTC_RIIR_AIF_Msk (1ul << RTC_RIIR_AIF_Pos)
/* RTC TTR Bit Field Definitions */
#define RTC_TTR_TWKE_Pos 3
#define RTC_TTR_TWKE_Msk (1ul << RTC_TTR_TWKE_Pos)
#define RTC_TTR_TTR_Pos 0
#define RTC_TTR_TTR_Msk (0x7ul << RTC_TTR_TTR_Pos)
/*---------------------------- Clock Controller ------------------------------*/
typedef struct
{
__IO uint32_t XTL12M_EN:1;
__IO uint32_t XTL32K_EN:1;
__IO uint32_t OSC22M_EN:1;
__IO uint32_t OSC10K_EN:1;
__IO uint32_t PD_WU_DLY:1;
__IO uint32_t PD_WU_INT_EN:1;
__IO uint32_t PD_WU_STS:1;
__IO uint32_t PWR_DOWN_EN:1;
__IO uint32_t PD_WAIT_CPU:1;
__I uint32_t RESERVE:23;
} SYSCLK_PWRCON_T;
typedef struct
{
__I uint32_t RESERVE0:2;
__IO uint32_t ISP_EN:1;
__I uint32_t RESERVE1:29;
} SYSCLK_AHBCLK_T;
typedef struct
{
__IO uint32_t WDT_EN:1;
__IO uint32_t RTC_EN:1;
__IO uint32_t TMR0_EN:1;
__IO uint32_t TMR1_EN:1;
__IO uint32_t TMR2_EN:1;
__IO uint32_t TMR3_EN:1;
__I uint32_t RESERVE0:3;
__IO uint32_t I2C_EN:1;
__I uint32_t RESERVE1:2;
__IO uint32_t SPI0_EN:1;
__IO uint32_t SPI1_EN:1;
__I uint32_t RESERVE2:2;
__IO uint32_t UART0_EN:1;
__IO uint32_t UART1_EN:1;
__I uint32_t RESERVE3:2;
__IO uint32_t PWM01_EN:1;
__IO uint32_t PWM23_EN:1;
__I uint32_t RESERVE4:5;
__IO uint32_t USBD_EN:1;
__I uint32_t RESERVE5:3;
__IO uint32_t PS2_EN:1;
} SYSCLK_APBCLK_T;
typedef struct
{
__I uint32_t XTL12M_STB:1;
__I uint32_t XTL32K_STB:1;
__I uint32_t PLL_STB:1;
__I uint32_t OSC10K_STB:1;
__I uint32_t OSC22M_STB:1;
__I uint32_t RESERVE0:2;
__IO uint32_t CLK_SW_FAIL:1;
__I uint32_t RESERVE1:24;
} SYSCLK_CLKSTATUS_T;
typedef struct
{
__IO uint32_t HCLK_S:3;
__IO uint32_t STCLK_S:3;
__I uint32_t RESERVE:26;
} SYSCLK_CLKSEL0_T;
typedef struct
{
__IO uint32_t WDT_S:2;
__I uint32_t RESERVE1:6;
__IO uint32_t TMR0_S:3;
__I uint32_t RESERVE2:1;
__IO uint32_t TMR1_S:3;
__I uint32_t RESERVE3:1;
__IO uint32_t TMR2_S:3;
__I uint32_t RESERVE4:1;
__IO uint32_t TMR3_S:3;
__I uint32_t RESERVE5:1;
__IO uint32_t UART_S:2;
__I uint32_t RESERVE6:2;
__IO uint32_t PWM01_S:2;
__IO uint32_t PWM23_S:2;
} SYSCLK_CLKSEL1_T;
typedef struct
{
__IO uint32_t HCLK_N:4;
__IO uint32_t USB_N:4;
__IO uint32_t UART_N:4;
__I uint32_t RESERVE:20;
} SYSCLK_CLKDIV_T;
typedef struct
{
__IO uint32_t FB_DV:9;
__IO uint32_t IN_DV:5;
__IO uint32_t OUT_DV:2;
__IO uint32_t PD:1;
__IO uint32_t BP:1;
__IO uint32_t OE:1;
__IO uint32_t PLL_SRC:1;
__I uint32_t RESERVE:12;
} SYSCLK_PLLCON_T;
typedef struct
{
union
{
__IO uint32_t u32PWRCON;
struct
{
__IO uint32_t XTL12M_EN:1;
__IO uint32_t XTL32K_EN:1;
__IO uint32_t OSC22M_EN:1;
__IO uint32_t OSC10K_EN:1;
__IO uint32_t PD_WU_DLY:1;
__IO uint32_t PD_WU_INT_EN:1;
__IO uint32_t PD_WU_STS:1;
__IO uint32_t PWR_DOWN_EN:1;
__IO uint32_t PD_WAIT_CPU:1;
__I uint32_t RESERVE:23;
} PWRCON;
};
union
{
__IO uint32_t u32AHBCLK;
struct
{
__I uint32_t RESERVE0:2;
__IO uint32_t ISP_EN:1;
__I uint32_t RESERVE1:29;
} AHBCLK;
};
union
{
__IO uint32_t u32APBCLK;
struct
{
__IO uint32_t WDT_EN:1;
__IO uint32_t RTC_EN:1;
__IO uint32_t TMR0_EN:1;
__IO uint32_t TMR1_EN:1;
__IO uint32_t TMR2_EN:1;
__IO uint32_t TMR3_EN:1;
__I uint32_t RESERVE0:3;
__IO uint32_t I2C_EN:1;
__I uint32_t RESERVE1:2;
__IO uint32_t SPI0_EN:1;
__IO uint32_t SPI1_EN:1;
__I uint32_t RESERVE2:2;
__IO uint32_t UART0_EN:1;
__IO uint32_t UART1_EN:1;
__I uint32_t RESERVE3:2;
__IO uint32_t PWM01_EN:1;
__IO uint32_t PWM23_EN:1;
__I uint32_t RESERVE4:5;
__IO uint32_t USBD_EN:1;
__I uint32_t RESERVE5:3;
__IO uint32_t PS2_EN:1;
} APBCLK;
};
union
{
__IO uint32_t u32CLKSTATUS;
struct
{
__I uint32_t XTL12M_STB:1;
__I uint32_t XTL32K_STB:1;
__I uint32_t PLL_STB:1;
__I uint32_t OSC10K_STB:1;
__I uint32_t OSC22M_STB:1;
__I uint32_t RESERVE0:2;
__IO uint32_t CLK_SW_FAIL:1;
__I uint32_t RESERVE1:24;
} CLKSTATUS;
};
union
{
__IO uint32_t u32CLKSEL0;
struct
{
__IO uint32_t HCLK_S:3;
__IO uint32_t STCLK_S:3;
__I uint32_t RESERVE:26;
} CLKSEL0;
};
union
{
__IO uint32_t u32CLKSEL1;
struct
{
__IO uint32_t WDT_S:2;
__I uint32_t RESERVE1:6;
__IO uint32_t TMR0_S:3;
__I uint32_t RESERVE2:1;
__IO uint32_t TMR1_S:3;
__I uint32_t RESERVE3:1;
__IO uint32_t TMR2_S:3;
__I uint32_t RESERVE4:1;
__IO uint32_t TMR3_S:3;
__I uint32_t RESERVE5:1;
__IO uint32_t UART_S:2;
__I uint32_t RESERVE6:2;
__IO uint32_t PWM01_S:2;
__IO uint32_t PWM23_S:2;
} CLKSEL1;
};
union
{
__IO uint32_t u32CLKDIV;
struct
{
__IO uint32_t HCLK_N:4;
__IO uint32_t USB_N:4;
__IO uint32_t UART_N:4;
__I uint32_t RESERVE:20;
} CLKDIV;
};
uint32_t RESERVE;
union
{
__IO uint32_t u32PLLCON;
struct
{
__IO uint32_t FB_DV:9;
__IO uint32_t IN_DV:5;
__IO uint32_t OUT_DV:2;
__IO uint32_t PD:1;
__IO uint32_t BP:1;
__IO uint32_t OE:1;
__IO uint32_t PLL_SRC:1;
__I uint32_t RESERVE:12;
} PLLCON;
};
} SYSCLK_T;
/* SYSCLK PWRCON Bit Field Definitions */
#define SYSCLK_PWRCON_PD_WAIT_CPU_Pos 8
#define SYSCLK_PWRCON_PD_WAIT_CPU_Msk (1ul << SYSCLK_PWRCON_PD_WAIT_CPU_Pos)
#define SYSCLK_PWRCON_PWR_DOWN_EN_Pos 7
#define SYSCLK_PWRCON_PWR_DOWN_EN_Msk (1ul << SYSCLK_PWRCON_PWR_DOWN_EN_Pos)
#define SYSCLK_PWRCON_PD_WU_STS_Pos 6
#define SYSCLK_PWRCON_PD_WU_STS_Msk (1ul << SYSCLK_PWRCON_PD_WU_STS_Pos)
#define SYSCLK_PWRCON_PD_WU_INT_EN_Pos 5
#define SYSCLK_PWRCON_PD_WU_INT_EN_Msk (1ul << SYSCLK_PWRCON_PD_WU_INT_EN_Pos)
#define SYSCLK_PWRCON_PD_WU_DLY_Pos 4
#define SYSCLK_PWRCON_PD_WU_DLY_Msk (1ul << SYSCLK_PWRCON_PD_WU_DLY_Pos)
#define SYSCLK_PWRCON_OSC10K_EN_Pos 3
#define SYSCLK_PWRCON_OSC10K_EN_Msk (1ul << SYSCLK_PWRCON_OSC10K_EN_Pos)
#define SYSCLK_PWRCON_OSC22M_EN_Pos 2
#define SYSCLK_PWRCON_OSC22M_EN_Msk (1ul << SYSCLK_PWRCON_OSC22M_EN_Pos)
#define SYSCLK_PWRCON_XTL32K_EN_Pos 1
#define SYSCLK_PWRCON_XTL32K_EN_Msk (1ul << SYSCLK_PWRCON_XTL32K_EN_Pos)
#define SYSCLK_PWRCON_XTL12M_EN_Pos 0
#define SYSCLK_PWRCON_XTL12M_EN_Msk (1ul << SYSCLK_PWRCON_XTL12M_EN_Pos)
/* SYSCLK AHBCLK Bit Field Definitions */
#define SYSCLK_AHBCLK_ISP_EN_Pos 2
#define SYSCLK_AHBCLK_ISP_EN_Msk (1ul << SYSCLK_AHBCLK_ISP_EN_Pos)
/* SYSCLK APBCLK Bit Field Definitions */
#define SYSCLK_APBCLK_PS2_EN_Pos 31
#define SYSCLK_APBCLK_PS2_EN_Msk (1ul << SYSCLK_APBCLK_PS2_EN_Pos)
#define SYSCLK_APBCLK_USBD_EN_Pos 27
#define SYSCLK_APBCLK_USBD_EN_Msk (1ul << SYSCLK_APBCLK_USBD_EN_Pos)
#define SYSCLK_APBCLK_PWM23_EN_Pos 21
#define SYSCLK_APBCLK_PWM23_EN_Msk (1ul << SYSCLK_APBCLK_PWM23_EN_Pos)
#define SYSCLK_APBCLK_PWM01_EN_Pos 20
#define SYSCLK_APBCLK_PWM01_EN_Msk (1ul << SYSCLK_APBCLK_PWM01_EN_Pos)
#define SYSCLK_APBCLK_UART1_EN_Pos 17
#define SYSCLK_APBCLK_UART1_EN_Msk (1ul << SYSCLK_APBCLK_UART1_EN_Pos)
#define SYSCLK_APBCLK_UART0_EN_Pos 16
#define SYSCLK_APBCLK_UART0_EN_Msk (1ul << SYSCLK_APBCLK_UART0_EN_Pos)
#define SYSCLK_APBCLK_SPI1_EN_Pos 13
#define SYSCLK_APBCLK_SPI1_EN_Msk (1ul << SYSCLK_APBCLK_SPI1_EN_Pos)
#define SYSCLK_APBCLK_SPI0_EN_Pos 12
#define SYSCLK_APBCLK_SPI0_EN_Msk (1ul << SYSCLK_APBCLK_SPI0_EN_Pos)
#define SYSCLK_APBCLK_I2C_EN_Pos 9
#define SYSCLK_APBCLK_I2C_EN_Msk (1ul << SYSCLK_APBCLK_I2C1_EN_Pos)
#define SYSCLK_APBCLK_TMR3_EN_Pos 5
#define SYSCLK_APBCLK_TMR3_EN_Msk (1ul << SYSCLK_APBCLK_TMR3_EN_Pos)
#define SYSCLK_APBCLK_TMR2_EN_Pos 4
#define SYSCLK_APBCLK_TMR2_EN_Msk (1ul << SYSCLK_APBCLK_TMR2_EN_Pos)
#define SYSCLK_APBCLK_TMR1_EN_Pos 3
#define SYSCLK_APBCLK_TMR1_EN_Msk (1ul << SYSCLK_APBCLK_TMR1_EN_Pos)
#define SYSCLK_APBCLK_TMR0_EN_Pos 2
#define SYSCLK_APBCLK_TMR0_EN_Msk (1ul << SYSCLK_APBCLK_TMR0_EN_Pos)
#define SYSCLK_APBCLK_RTC_EN_Pos 1
#define SYSCLK_APBCLK_RTC_EN_Msk (1ul << SYSCLK_APBCLK_RTC_EN_Pos)
#define SYSCLK_APBCLK_WDT_EN_Pos 0
#define SYSCLK_APBCLK_WDT_EN_Msk (1ul << SYSCLK_APBCLK_WDT_EN_Pos)
/* SYSCLK CLKSTATUS Bit Field Definitions */
#define SYSCLK_CLKSTATUS_CLK_SW_FAIL_Pos 7
#define SYSCLK_CLKSTATUS_CLK_SW_FAIL_Msk (1ul << SYSCLK_CLKSTATUS_CLK_SW_FAIL_Pos)
#define SYSCLK_CLKSTATUS_OSC22M_STB_Pos 4
#define SYSCLK_CLKSTATUS_OSC22M_STB_Msk (1ul << SYSCLK_CLKSTATUS_OSC22M_STB_Pos)
#define SYSCLK_CLKSTATUS_OSC10K_STB_Pos 3
#define SYSCLK_CLKSTATUS_OSC10K_STB_Msk (1ul << SYSCLK_CLKSTATUS_OSC10K_STB_Pos)
#define SYSCLK_CLKSTATUS_PLL_STB_Pos 2
#define SYSCLK_CLKSTATUS_PLL_STB_Msk (1ul << SYSCLK_CLKSTATUS_PLL_STB_Pos)
#define SYSCLK_CLKSTATUS_XTL32K_STB_Pos 1
#define SYSCLK_CLKSTATUS_XTL32K_STB_Msk (1ul << SYSCLK_CLKSTATUS_XTL32K_STB_Pos)
#define SYSCLK_CLKSTATUS_XTL12M_STB_Pos 0
#define SYSCLK_CLKSTATUS_XTL12M_STB_Msk (1ul << SYSCLK_CLKSTATUS_XTL12M_STB_Pos)
/* SYSCLK CLKSEL0 Bit Field Definitions */
#define SYSCLK_CLKSEL0_STCLK_S_Pos 3
#define SYSCLK_CLKSEL0_STCLK_S_Msk (7ul << SYSCLK_CLKSEL0_STCLK_S_Pos)
#define SYSCLK_CLKSEL0_HCLK_S_Pos 0
#define SYSCLK_CLKSEL0_HCLK_S_Msk (7ul << SYSCLK_CLKSEL0_HCLK_S_Pos)
/* SYSCLK CLKSEL1 Bit Field Definitions */
#define SYSCLK_CLKSEL1_PWM23_S_Pos 30
#define SYSCLK_CLKSEL1_PWM23_S_Msk (3ul << SYSCLK_CLKSEL1_PWM23_S_Pos)
#define SYSCLK_CLKSEL1_PWM01_S_Pos 28
#define SYSCLK_CLKSEL1_PWM01_S_Msk (3ul << SYSCLK_CLKSEL1_PWM01_S_Pos)
#define SYSCLK_CLKSEL1_UART_S_Pos 24
#define SYSCLK_CLKSEL1_UART_S_Msk (3ul << SYSCLK_CLKSEL1_UART_S_Pos)
#define SYSCLK_CLKSEL1_TMR3_S_Pos 20
#define SYSCLK_CLKSEL1_TMR3_S_Msk (7ul << SYSCLK_CLKSEL1_TMR3_S_Pos)
#define SYSCLK_CLKSEL1_TMR2_S_Pos 16
#define SYSCLK_CLKSEL1_TMR2_S_Msk (7ul << SYSCLK_CLKSEL1_TMR2_S_Pos)
#define SYSCLK_CLKSEL1_TMR1_S_Pos 12
#define SYSCLK_CLKSEL1_TMR1_S_Msk (7ul << SYSCLK_CLKSEL1_TMR1_S_Pos)
#define SYSCLK_CLKSEL1_TMR0_S_Pos 8
#define SYSCLK_CLKSEL1_TMR0_S_Msk (7ul << SYSCLK_CLKSEL1_TMR0_S_Pos)
#define SYSCLK_CLKSEL1_WDT_S_Pos 0
#define SYSCLK_CLKSEL1_WDT_S_Msk (3ul << SYSCLK_CLKSEL1_WDT_S_Pos)
/* SYSCLK CLKDIV Bit Field Definitions */
#define SYSCLK_CLKDIV_UART_N_Pos 8
#define SYSCLK_CLKDIV_UART_N_Msk (0xFul << SYSCLK_CLKDIV_UART_N_Pos)
#define SYSCLK_CLKDIV_USB_N_Pos 4
#define SYSCLK_CLKDIV_USB_N_Msk (0xFul << SYSCLK_CLKDIV_USB_N_Pos)
#define SYSCLK_CLKDIV_HCLK_N_Pos 0
#define SYSCLK_CLKDIV_HCLK_N_Msk (0xFul << SYSCLK_CLKDIV_HCLK_N_Pos)
/* SYSCLK PLLCON Bit Field Definitions */
#define SYSCLK_PLLCON_PLL_SRC_Pos 19
#define SYSCLK_PLLCON_PLL_SRC_Msk (1ul << SYSCLK_PLLCON_PLL_SRC_Pos)
#define SYSCLK_PLLCON_OE_Pos 18
#define SYSCLK_PLLCON_OE_Msk (1ul << SYSCLK_PLLCON_OE_Pos)
#define SYSCLK_PLLCON_BP_Pos 17
#define SYSCLK_PLLCON_BP_Msk (1ul << SYSCLK_PLLCON_BP_Pos)
#define SYSCLK_PLLCON_PD_Pos 16
#define SYSCLK_PLLCON_PD_Msk (1ul << SYSCLK_PLLCON_PD_Pos)
#define SYSCLK_PLLCON_OUT_DV_Pos 14
#define SYSCLK_PLLCON_OUT_DV_Msk (3ul << SYSCLK_PLLCON_OUT_DV_Pos)
#define SYSCLK_PLLCON_IN_DV_Pos 9
#define SYSCLK_PLLCON_IN_DV_Msk (0x1Ful << SYSCLK_PLLCON_IN_DV_Pos)
#define SYSCLK_PLLCON_FB_DV_Pos 0
#define SYSCLK_PLLCON_FB_DV_Msk (0x1FFul << SYSCLK_PLLCON_FB_DV_Pos)
/*---------------------------- Global Controller -----------------------------*/
typedef __I uint32_t GCR_PDID_T;
typedef struct
{
__IO uint32_t RSTS_POR:1;
__IO uint32_t RSTS_RESET:1;
__IO uint32_t RSTS_WDT:1;
__IO uint32_t RSTS_LVR:1;
__IO uint32_t RSTS_BOD:1;
__IO uint32_t RSTS_SYS:1;
__I uint32_t RESERVE0:1;
__IO uint32_t RSTS_CPU:1;
__I uint32_t RESERVE1:24;
} GCR_RSTSRC_T;
typedef struct
{
__IO uint32_t CHIP_RST:1;
__IO uint32_t CPU_RST:1;
__I uint32_t RESERVE:30;
} GCR_IPRSTC1_T;
typedef struct
{
__I uint32_t RESERVE0:1;
__IO uint32_t GPIO_RST:1;
__IO uint32_t TMR0_RST:1;
__IO uint32_t TMR1_RST:1;
__IO uint32_t TMR2_RST:1;
__IO uint32_t TMR3_RST:1;
__I uint32_t RESERVE1:3;
__IO uint32_t I2C_RST:1;
__I uint32_t RESERVE2:2;
__IO uint32_t SPI0_RST:1;
__IO uint32_t SPI1_RST:1;
__I uint32_t RESERVE3:2;
__IO uint32_t UART0_RST:1;
__IO uint32_t UART1_RST:1;
__I uint32_t RESERVE4:2;
__IO uint32_t PWM03_RST:1;
__I uint32_t RESERVE5:2;
__IO uint32_t PS2_RST:1;
__I uint32_t RESERVE6:3;
__IO uint32_t USBD_RST:1;
__I uint32_t RESERVE7:4;
} GCR_IPRSTC2_T;
typedef struct
{
__IO uint32_t HPE:1;
__I uint32_t RESERVE:31;
} GCR_CPR_T;
typedef struct
{
__IO uint32_t BOD_EN:1;
__IO uint32_t BOD_VL:2;
__IO uint32_t BOD_RSTEN:1;
__IO uint32_t BOD_INTF:1;
__IO uint32_t BOD_LPM:1;
__IO uint32_t BOD_OUT:1;
__IO uint32_t LVR_EN:1;
__I uint32_t RESERVE1:24;
} GCR_BODCR_T;
typedef __IO uint32_t GCR_PORCR_T;
typedef struct
{
__I uint32_t RESERVE:10;
__IO uint32_t I2C_SDA:1;
__IO uint32_t I2C_SCL:1;
__IO uint32_t PWM0:1;
__IO uint32_t PWM1:1;
__IO uint32_t PWM2:1;
__IO uint32_t PWM3:1;
__IO uint32_t SCHMITT:16;
} GCR_GPAMFP_T;
typedef struct
{
__IO uint32_t UART0_RX:1;
__IO uint32_t UART0_TX:1;
__IO uint32_t UART0_nRTS:1;
__IO uint32_t UART0_nCTS:1;
__IO uint32_t UART1_RX_SPI1_SS1:1;
__IO uint32_t UART1_TX:1;
__IO uint32_t UART1_nRTS_SPI1_CLK:1;
__IO uint32_t UART1_nCTS_SPI1_SS1:1;
__IO uint32_t TM0:1;
__IO uint32_t TM1_SS11:1;
__IO uint32_t TM2_SS01:1;
__I uint32_t RESERVE2:3;
__IO uint32_t INT0:1;
__IO uint32_t INT1:1;
__IO uint32_t SCHMITT:16;
} GCR_GPBMFP_T;
typedef struct
{
__IO uint32_t SPI0_SS0:1;
__IO uint32_t SPI0_CLK:1;
__IO uint32_t SPI0_MISO0:1;
__IO uint32_t SPI0_MOSI0:1;
__I uint32_t RESERVE0:4;
__IO uint32_t SPI1_SS0:1;
__IO uint32_t SPI1_CLK:1;
__IO uint32_t SPI1_MISO0:1;
__IO uint32_t SPI1_MOSI0:1;
__I uint32_t RESERVE1:4;
__IO uint32_t SCHMITT:16;
} GCR_GPCMFP_T;
typedef struct
{
__I uint32_t RESERVE0:1;
__IO uint32_t SPI0_SS1:1;
__I uint32_t RESERVE1:14;
__IO uint32_t SCHMITT:16;
} GCR_GPDMFP_T;
typedef struct
{
__IO uint32_t PB10_S01:1; /* GPB10 */
__IO uint32_t PB9_S11:1; /* GPB9 */
__I uint32_t RESERVE0:13;
__IO uint32_t UART1_RX_SPI1_SS1:1; /* GPB4 */
__I uint32_t RESERVE1:16;
} GCR_ALTMFP_T;
typedef __IO uint32_t GCR_REGWRPROT_T;
typedef struct
{
union
{
__I uint32_t u32PDID;
__I uint32_t PDID;
};
union
{
__IO uint32_t u32RSTSRC;
struct
{
__IO uint32_t RSTS_POR:1;
__IO uint32_t RSTS_RESET:1;
__IO uint32_t RSTS_WDT:1;
__IO uint32_t RSTS_LVR:1;
__IO uint32_t RSTS_BOD:1;
__IO uint32_t RSTS_SYS:1;
__I uint32_t RESERVE0:1;
__IO uint32_t RSTS_CPU:1;
__I uint32_t RESERVE1:24;
} RSTSRC;
};
union
{
__IO uint32_t u32IPRSTC1;
struct
{
__IO uint32_t CHIP_RST:1;
__IO uint32_t CPU_RST:1;
__I uint32_t RESERVE:30;
} IPRSTC1;
};
union
{
__IO uint32_t u32IPRSTC2;
struct
{
__I uint32_t RESERVE0:1;
__IO uint32_t GPIO_RST:1;
__IO uint32_t TMR0_RST:1;
__IO uint32_t TMR1_RST:1;
__IO uint32_t TMR2_RST:1;
__IO uint32_t TMR3_RST:1;
__I uint32_t RESERVE1:3;
__IO uint32_t I2C_RST:1;
__I uint32_t RESERVE2:2;
__IO uint32_t SPI0_RST:1;
__IO uint32_t SPI1_RST:1;
__I uint32_t RESERVE3:2;
__IO uint32_t UART0_RST:1;
__IO uint32_t UART1_RST:1;
__I uint32_t RESERVE4:2;
__IO uint32_t PWM03_RST:1;
__I uint32_t RESERVE5:2;
__IO uint32_t PS2_RST:1;
__I uint32_t RESERVE6:3;
__IO uint32_t USBD_RST:1;
__I uint32_t RESERVE7:4;
} IPRSTC2;
};
union
{
__IO uint32_t u32CPR;
struct
{
__IO uint32_t HPE:1;
__I uint32_t RESERVE:31;
} CPR;
};
uint32_t RESERVE0;
union
{
__IO uint32_t u32BODCR;
struct
{
__IO uint32_t BOD_EN:1;
__IO uint32_t BOD_VL:2;
__IO uint32_t BOD_RSTEN:1;
__IO uint32_t BOD_INTF:1;
__IO uint32_t BOD_LPM:1;
__IO uint32_t BOD_OUT:1;
__IO uint32_t LVR_EN:1;
__I uint32_t RESERVE1:24;
} BODCR;
};
uint32_t RESERVE1[2];
union
{
__IO uint32_t u32PORCR;
__IO uint32_t PORCR;
};
uint32_t RESERVE2[2];
union
{
__IO uint32_t u32GPAMFP;
struct
{
__I uint32_t RESERVE:10;
__IO uint32_t I2C_SDA:1;
__IO uint32_t I2C_SCL:1;
__IO uint32_t PWM0:1;
__IO uint32_t PWM1:1;
__IO uint32_t PWM2:1;
__IO uint32_t PWM3:1;
__IO uint32_t SCHMITT:16;
} GPAMFP;
};
union
{
__IO uint32_t u32GPBMFP;
struct
{
__IO uint32_t UART0_RX:1;
__IO uint32_t UART0_TX:1;
__IO uint32_t UART0_nRTS:1;
__IO uint32_t UART0_nCTS:1;
__IO uint32_t UART1_RX_SPI1_SS1:1;
__IO uint32_t UART1_TX:1;
__IO uint32_t UART1_nRTS_SPI1_CLK:1;
__IO uint32_t UART1_nCTS_SPI1_SS1:1;
__IO uint32_t TM0:1;
__IO uint32_t TM1_SS11:1;
__IO uint32_t TM2_SS01:1;
__I uint32_t RESERVE2:3;
__IO uint32_t INT0:1;
__IO uint32_t INT1:1;
__IO uint32_t SCHMITT:16;
} GPBMFP;
};
union
{
__IO uint32_t u32GPCMFP;
struct
{
__IO uint32_t SPI0_SS0:1;
__IO uint32_t SPI0_CLK:1;
__IO uint32_t SPI0_MISO0:1;
__IO uint32_t SPI0_MOSI0:1;
__I uint32_t RESERVE0:4;
__IO uint32_t SPI1_SS0:1;
__IO uint32_t SPI1_CLK:1;
__IO uint32_t SPI1_MISO0:1;
__IO uint32_t SPI1_MOSI0:1;
__I uint32_t RESERVE1:4;
__IO uint32_t SCHMITT:16;
} GPCMFP;
};
union
{
__IO uint32_t u32GPDMFP;
struct
{
__I uint32_t RESERVE0:1;
__IO uint32_t SPI0_SS1:1;
__I uint32_t RESERVE1:14;
__IO uint32_t SCHMITT:16;
} GPDMFP;
};
uint32_t RESERVE3[4];
union
{
__IO uint32_t u32ALTMFP;
struct
{
__IO uint32_t PB10_S01:1; /* GPB10 */
__IO uint32_t PB9_S11:1; /* GPB9 */
__I uint32_t RESERVE0:13;
__IO uint32_t UART1_RX_SPI1_SS1:1; /* GPB4 */
__I uint32_t RESERVE1:16;
} ALTMFP;
};
uint32_t RESERVE4[43];
union
{
__IO uint32_t u32REGWRPROT;
__IO uint32_t REGWRPROT;
};
} GCR_T;
/* GCR RSTSRC Bit Field Definitions */
#define GCR_RSTSRC_RSTS_CPU_Pos 7
#define GCR_RSTSRC_RSTS_CPU_Msk (1ul << GCR_RSTSRC_RSTS_CPU_Pos)
#define GCR_RSTSRC_RSTS_SYS_Pos 5
#define GCR_RSTSRC_RSTS_SYS_Msk (1ul << GCR_RSTSRC_RSTS_SYS_Pos)
#define GCR_RSTSRC_RSTS_BOD_Pos 4
#define GCR_RSTSRC_RSTS_BOD_Msk (1ul << GCR_RSTSRC_RSTS_BOD_Pos)
#define GCR_RSTSRC_RSTS_LVR_Pos 3
#define GCR_RSTSRC_RSTS_LVR_Msk (1ul << GCR_RSTSRC_RSTS_LVR_Pos)
#define GCR_RSTSRC_RSTS_WDT_Pos 2
#define GCR_RSTSRC_RSTS_WDT_Msk (1ul << GCR_RSTSRC_RSTS_WDT_Pos)
#define GCR_RSTSRC_RSTS_RESET_Pos 1
#define GCR_RSTSRC_RSTS_RESET_Msk (1ul << GCR_RSTSRC_RSTS_RESET_Pos)
#define GCR_RSTSRC_RSTS_POR_Pos 0
#define GCR_RSTSRC_RSTS_POR_Msk (1ul << GCR_RSTSRC_RSTS_POR_Pos)
/* GCR IPRSTC1 Bit Field Definitions */
#define GCR_IPRSTC1_CPU_RST_Pos 1
#define GCR_IPRSTC1_CPU_RST_Msk (1ul << GCR_IPRSTC1_CPU_RST_Pos)
#define GCR_IPRSTC1_CHIP_RST_Pos 0
#define GCR_IPRSTC1_CHIP_RST_Msk (1ul << GCR_IPRSTC1_CHIP_RST_Pos)
/* GCR IPRSTC2 Bit Field Definitions */
#define GCR_IPRSTC2_USBD_RST_Pos 27
#define GCR_IPRSTC2_USBD_RST_Msk (1ul << GCR_IPRSTC2_USBD_RST_Pos)
#define GCR_IPRSTC2_PS2_RST_Pos 23
#define GCR_IPRSTC2_PS2_RST_Msk (1ul << GCR_IPRSTC2_PS2_RST_Pos)
#define GCR_IPRSTC2_PWM03_RST_Pos 20
#define GCR_IPRSTC2_PWM03_RST_Msk (1ul << GCR_IPRSTC2_PWM03_RST_Pos)
#define GCR_IPRSTC2_UART1_RST_Pos 17
#define GCR_IPRSTC2_UART1_RST_Msk (1ul << GCR_IPRSTC2_UART1_RST_Pos)
#define GCR_IPRSTC2_UART0_RST_Pos 16
#define GCR_IPRSTC2_UART0_RST_Msk (1ul << GCR_IPRSTC2_UART0_RST_Pos)
#define GCR_IPRSTC2_SPI1_RST_Pos 13
#define GCR_IPRSTC2_SPI1_RST_Msk (1ul << GCR_IPRSTC2_SPI1_RST_Pos)
#define GCR_IPRSTC2_SPI0_RST_Pos 12
#define GCR_IPRSTC2_SPI0_RST_Msk (1ul << GCR_IPRSTC2_SPI0_RST_Pos)
#define GCR_IPRSTC2_I2C_RST_Pos 9
#define GCR_IPRSTC2_I2C_RST_Msk (1ul << GCR_IPRSTC2_I2C1_RST_Pos)
#define GCR_IPRSTC2_TMR3_RST_Pos 5
#define GCR_IPRSTC2_TMR3_RST_Msk (1ul << GCR_IPRSTC2_TMR3_RST_Pos)
#define GCR_IPRSTC2_TMR2_RST_Pos 4
#define GCR_IPRSTC2_TMR2_RST_Msk (1ul << GCR_IPRSTC2_TMR2_RST_Pos)
#define GCR_IPRSTC2_TMR1_RST_Pos 3
#define GCR_IPRSTC2_TMR1_RST_Msk (1ul << GCR_IPRSTC2_TMR1_RST_Pos)
#define GCR_IPRSTC2_TMR0_RST_Pos 2
#define GCR_IPRSTC2_TMR0_RST_Msk (1ul << GCR_IPRSTC2_TMR0_RST_Pos)
#define GCR_IPRSTC2_GPIO_RST_Pos 1
#define GCR_IPRSTC2_GPIO_RST_Msk (1ul << GCR_IPRSTC2_GPIO_RST_Pos)
/* GCR CPR Bit Field Definitions */
#define GCR_CPR_HPE_Pos 0
#define GCR_CPR_HPE_Msk (1ul << GCR_CPR_HPE_Pos)
/* GCR BODCR Bit Field Definitions */
#define GCR_BODCR_LVR_EN_Pos 7
#define GCR_BODCR_LVR_EN_Msk (1ul << GCR_BODCR_LVR_EN_Pos)
#define GCR_BODCR_BOD_OUT_Pos 6
#define GCR_BODCR_BOD_OUT_Msk (1ul << GCR_BODCR_BOD_OUT_Pos)
#define GCR_BODCR_BOD_LPM_Pos 5
#define GCR_BODCR_BOD_LPM_Msk (1ul << GCR_BODCR_BOD_LPM_Pos)
#define GCR_BODCR_BOD_INTF_Pos 4
#define GCR_BODCR_BOD_INTF_Msk (1ul << GCR_BODCR_BOD_INTF_Pos)
#define GCR_BODCR_BOD_RSTEN_Pos 3
#define GCR_BODCR_BOD_RSTEN_Msk (1ul << GCR_BODCR_BOD_RSTEN_Pos)
#define GCR_BODCR_BOD_VL_Pos 1
#define GCR_BODCR_BOD_VL_Msk (3ul << GCR_BODCR_BOD_VL_Pos)
#define GCR_BODCR_BOD_EN_Pos 0
#define GCR_BODCR_BOD_EN_Msk (1ul << GCR_BODCR_BOD_EN_Pos)
/* GCR TEMPCR Bit Field Definitions */
#define GCR_TEMPCR_VTEMP_EN_Pos 0
#define GCR_TEMPCR_VTEMP_EN_Msk (1ul << GCR_TEMPCR_VTEMP_EN_Pos)
/* GCR PORCR Bit Field Definitions */
#define GCR_PORCR_POR_DIS_CODE_Pos 0
#define GCR_PORCR_POR_DIS_CODE_Msk (0xFFFFul << GCR_PORCR_POR_DIS_CODE_Pos)
/* GCR GPAMFP Bit Field Definitions */
#define GCR_GPAMFP_GPA_TYPE_Pos 16
#define GCR_GPAMFP_GPA_TYPE_Msk (0xFFFFul << GCR_GPAMFP_GPA_TYPE_Pos)
#define GCR_GPAMFP_GPA_MFP_Pos 0
#define GCR_GPAMFP_GPA_MFP_Msk (0xFFFFul << GCR_GPAMFP_GPA_MFP_Pos)
/* GCR GPBMFP Bit Field Definitions */
#define GCR_GPBMFP_GPB_TYPE_Pos 16
#define GCR_GPBMFP_GPB_TYPE_Msk (0xFFFFul << GCR_GPBMFP_GPB_TYPE_Pos)
#define GCR_GPBMFP_GPB_MFP_Pos 0
#define GCR_GPBMFP_GPB_MFP_Msk (0xFFFFul << GCR_GPBMFP_GPB_MFP_Pos)
/* GCR GPCMFP Bit Field Definitions */
#define GCR_GPCMFP_GPC_TYPE_Pos 16
#define GCR_GPCMFP_GPC_TYPE_Msk (0xFFFFul << GCR_GPCMFP_GPC_TYPE_Pos)
#define GCR_GPCMFP_GPC_MFP_Pos 0
#define GCR_GPCMFP_GPC_MFP_Msk (0xFFFFul << GCR_GPCMFP_GPC_MFP_Pos)
/* GCR GPDMFP Bit Field Definitions */
#define GCR_GPDMFP_GPD_TYPE_Pos 16
#define GCR_GPDMFP_GPD_TYPE_Msk (0xFFFFul << GCR_GPDMFP_GPD_TYPE_Pos)
#define GCR_GPDMFP_GPD_MFP_Pos 0
#define GCR_GPDMFP_GPD_MFP_Msk (0xFFFFul << GCR_GPDMFP_GPD_MFP_Pos)
/* GCR ALTMFP Bit Field Definitions */
#define GCR_ALTMFP_PB4_S11_Pos 15
#define GCR_ALTMFP_PB4_S11_Msk (1ul << GCR_ALTMFP_PB4_S11_Pos)
#define GCR_ALTMFP_PB9_S11_Pos 1
#define GCR_ALTMFP_PB9_S11_Msk (1ul << GCR_ALTMFP_PB9_S11_Pos)
#define GCR_ALTMFP_PB10_S01_Pos 0
#define GCR_ALTMFP_PB10_S01_Msk (1ul << GCR_ALTMFP_PB10_S01_Pos)
/* GCR REGWRPROT Bit Field Definitions */
#define GCR_REGWRPROT_REGWRPROT_Pos 0
#define GCR_REGWRPROT_REGWRPROT_Msk (0xFFul << GCR_REGWRPROT_REGWRPROT_Pos)
typedef struct
{
__IO uint32_t INTSRC:4;
__I uint32_t RESERVE:28;
} GCR_IRQSRC_T;
typedef struct
{
__IO uint32_t NMISEL:5;
__I uint32_t RESERVE0:2;
__IO uint32_t INT_TEST:1;
__I uint32_t RESERVE1:24;
} GCR_NMISEL_T;
typedef __IO uint32_t GCR_MCUIRQ_T;
typedef struct
{
union
{
__I uint32_t u32IRQSRC[32];
__I uint32_t IRQSRC[32];
};
union
{
__IO uint32_t u32NMISEL;
struct
{
__IO uint32_t NMISEL:5;
__I uint32_t RESERVE0:2;
__IO uint32_t INT_TEST:1;
__I uint32_t RESERVE1:24;
} NMISEL;
};
union
{
__IO uint32_t u32MCUIRQ;
__IO uint32_t MCUIRQ;
};
} GCR_INT_T;
/* GCR IRQSRC Bit Field Definitions */
#define GCR_IRQSRC_INT_SRC_Pos 0
#define GCR_IRQSRC_INT_SRC_Msk (0xFul << GCR_IRQSRC_INT_SRC_Pos)
/* GCR NMISEL Bit Field Definitions */
#define GCR_NMISEL_INT_TEST_Pos 7
#define GCR_NMISEL_INT_TEST_Msk (1ul << GCR_NMISEL_INT_TEST_Pos)
#define GCR_NMISEL_NMISEL_Pos 0
#define GCR_NMISEL_NMISEL_Msk (0x1Ful << GCR_NMISEL_NMISEL_Pos)
/*-------------------------- FLASH Memory Controller -------------------------*/
typedef struct
{
__IO uint32_t ISPEN:1;
__IO uint32_t BS:1;
__I uint32_t RESERVE0:2;
__IO uint32_t CFGUEN:1;
__IO uint32_t LDUEN:1;
__IO uint32_t ISPFF:1;
__I uint32_t RESERVE1:1;
__IO uint32_t PT:3;
__I uint32_t RESERVE2:1;
__IO uint32_t ET:3;
__I uint32_t RESERVE3:17;
} FMC_ISPCON_T;
typedef __IO uint32_t FMC_ISPADR_T;
typedef __IO uint32_t FMC_ISPDAT_T;
typedef struct
{
__IO uint32_t FCTRL:4;
__IO uint32_t FCEN:1;
__IO uint32_t FOEN:1;
__I uint32_t RESERVE:26;
} FMC_ISPCMD_T;
typedef struct
{
__IO uint32_t ISPGO:1;
__I uint32_t RESERVE:31;
} FMC_ISPTRG_T;
typedef __I uint32_t FMC_DFBADR_T;
typedef struct
{
__I uint32_t RESERVE0:4;
__IO uint32_t LFOM:1;
__I uint32_t RESERVE1:1;
__IO uint32_t MFOM:1;
__I uint32_t RESERVE2:25;
} FMC_FATCON_T;
typedef struct
{
union
{
__IO uint32_t u32ISPCON;
struct
{
__IO uint32_t ISPEN:1;
__IO uint32_t BS:1;
__I uint32_t RESERVE0:2;
__IO uint32_t CFGUEN:1;
__IO uint32_t LDUEN:1;
__IO uint32_t ISPFF:1;
__I uint32_t RESERVE1:1;
__IO uint32_t PT:3;
__I uint32_t RESERVE2:1;
__IO uint32_t ET:3;
__I uint32_t RESERVE3:17;
} ISPCON;
};
union
{
__IO uint32_t u32ISPADR;
__IO uint32_t ISPADR;
};
union
{
__IO uint32_t u32ISPDAT;
__IO uint32_t ISPDAT;
};
union
{
__IO uint32_t u32ISPCMD;
struct
{
__IO uint32_t FCTRL:4;
__IO uint32_t FCEN:1;
__IO uint32_t FOEN:1;
__I uint32_t RESERVE:26;
} ISPCMD;
};
union
{
__IO uint32_t u32ISPTRG;
struct
{
__IO uint32_t ISPGO:1;
__I uint32_t RESERVE:31;
} ISPTRG;
};
union
{
__I uint32_t u32DFBADR;
__I uint32_t DFBADR;
};
union
{
__IO uint32_t u32FATCON;
struct
{
__I uint32_t RESERVE0:4;
__IO uint32_t LFOM:1;
__I uint32_t RESERVE1:1;
__IO uint32_t MFOM:1;
__I uint32_t RESERVE2:25;
} FATCON;
};
} FMC_T;
/* FMC ISPCON Bit Field Definitions */
#define FMC_ISPCON_ET_Pos 12
#define FMC_ISPCON_ET_Msk (7ul << FMC_ISPCON_ET_Pos)
#define FMC_ISPCON_PT_Pos 8
#define FMC_ISPCON_PT_Msk (7ul << FMC_ISPCON_PT_Pos)
#define FMC_ISPCON_ISPFF_Pos 6
#define FMC_ISPCON_ISPFF_Msk (1ul << FMC_ISPCON_ISPFF_Pos)
#define FMC_ISPCON_LDUEN_Pos 5
#define FMC_ISPCON_LDUEN_Msk (1ul << FMC_ISPCON_LDUEN_Pos)
#define FMC_ISPCON_CFGUEN_Pos 4
#define FMC_ISPCON_CFGUEN_Msk (1ul << FMC_ISPCON_CFGUEN_Pos)
#define FMC_ISPCON_BS_Pos 1
#define FMC_ISPCON_BS_Msk (1ul << FMC_ISPCON_BS_Pos)
#define FMC_ISPCON_ISPEN_Pos 0
#define FMC_ISPCON_ISPEN_Msk (1ul << FMC_ISPCON_ISPEN_Pos)
/* FMC ISPADR Bit Field Definitions */
#define FMC_ISPADR_ISPADR_Pos 0
#define FMC_ISPADR_ISPADR_Msk (0xFFFFFFFFul << FMC_ISPADR_ISPADR_Pos)
/* FMC ISPADR Bit Field Definitions */
#define FMC_ISPDAT_ISPDAT_Pos 0
#define FMC_ISPDAT_ISPDAT_Msk (0xFFFFFFFFul << FMC_ISPDAT_ISPDAT_Pos)
/* FMC ISPCMD Bit Field Definitions */
#define FMC_ISPCMD_FOEN_Pos 5
#define FMC_ISPCMD_FOEN_Msk (1ul << FMC_ISPCMD_FOEN_Pos)
#define FMC_ISPCMD_FCEN_Pos 4
#define FMC_ISPCMD_FCEN_Msk (1ul << FMC_ISPCMD_FCEN_Pos)
#define FMC_ISPCMD_FCTRL_Pos 0
#define FMC_ISPCMD_FCTRL_Msk (0xFul << FMC_ISPCMD_FCTRL_Pos)
/* FMC ISPTRG Bit Field Definitions */
#define FMC_ISPTRG_ISPGO_Pos 0
#define FMC_ISPTRG_ISPGO_Msk (1ul << FMC_ISPTRG_ISPGO_Pos)
/* FMC DFBADR Bit Field Definitions */
#define FMC_DFBADR_DFBA_Pos 0
#define FMC_DFBADR_DFBA_Msk (0xFFFFFFFFul << FMC_DFBADR_DFBA_Pos)
/* FMC FATCON Bit Field Definitions */
#define FMC_FATCON_MFOM_Pos 6
#define FMC_FATCON_MFOM_Msk (1ul << FMC_FATCON_MFOM_Pos)
#define FMC_FATCON_LFOM_Pos 4
#define FMC_FATCON_LFOM_Msk (1ul << FMC_FATCON_LFOM_Pos)
/*------------------------ PS2 Device Interface Controller -------------------*/
typedef struct
{
__IO uint32_t PS2EN:1;
__IO uint32_t TXINTEN:1;
__IO uint32_t RXINTEN:1;
__IO uint32_t TXFIFO_DEPTH:4;
__IO uint32_t ACK:1;
__IO uint32_t CLRFIFO:1;
__IO uint32_t OVERRIDE:1;
__IO uint32_t FPS2CLK:1;
__IO uint32_t FPS2DAT:1;
__I uint32_t RESERVE:20;
} PS2_CON_T;
typedef __IO uint32_t PS2_DATA_T;
typedef struct
{
__IO uint32_t PS2CLK:1;
__IO uint32_t PS2DATA:1;
__IO uint32_t FRAMERR:1;
__IO uint32_t RXPARTY:1;
__IO uint32_t RXBUSY:1;
__IO uint32_t TXBUSY:1;
__IO uint32_t RXOVF:1;
__IO uint32_t TXEMPTY:1;
__IO uint32_t BYTEIDX:4;
__I uint32_t RESERVE:20;
} PS2_STATUS_T;
typedef struct
{
__IO uint32_t RXINT:1;
__IO uint32_t TXINT:1;
__I uint32_t RESERVE:30;
} PS2_INTID_T;
typedef struct
{
union
{
__IO uint32_t u32PS2CON;
struct
{
__IO uint32_t PS2EN:1;
__IO uint32_t TXINTEN:1;
__IO uint32_t RXINTEN:1;
__IO uint32_t TXFIFO_DEPTH:4;
__IO uint32_t ACK:1;
__IO uint32_t CLRFIFO:1;
__IO uint32_t OVERRIDE:1;
__IO uint32_t FPS2CLK:1;
__IO uint32_t FPS2DAT:1;
__I uint32_t RESERVE:20;
} PS2CON;
};
union
{
__IO uint32_t u32TXDATA[4];
__IO uint32_t TXDATA[4];
};
union
{
__I uint32_t u32RXDATA;
__I uint32_t RXDATA;
};
union
{
__IO uint32_t u32STATUS;
struct
{
__IO uint32_t PS2CLK:1;
__IO uint32_t PS2DATA:1;
__IO uint32_t FRAMERR:1;
__IO uint32_t RXPARTY:1;
__IO uint32_t RXBUSY:1;
__IO uint32_t TXBUSY:1;
__IO uint32_t RXOVF:1;
__IO uint32_t TXEMPTY:1;
__IO uint32_t BYTEIDX:4;
__I uint32_t RESERVE:20;
} STATUS;
};
union
{
__IO uint32_t u32INTID;
struct
{
__IO uint32_t RXINT:1;
__IO uint32_t TXINT:1;
__I uint32_t RESERVE:30;
} INTID;
};
} PS2_T;
/* PS/2 PS2CON Bit Field Definitions */
#define PS2_PS2CON_PS2EN_Pos 0
#define PS2_PS2CON_PS2EN_Msk (1ul << PS2_PS2CON_PS2EN_Pos)
#define PS2_PS2CON_TXINTEN_Pos 1
#define PS2_PS2CON_TXINTEN_Msk (1ul << PS2_PS2CON_TXINTEN_Pos)
#define PS2_PS2CON_RXINTEN_Pos 2
#define PS2_PS2CON_RXINTEN_Msk (1ul << PS2_PS2CON_RXINTEN_Pos)
#define PS2_PS2CON_TXFIFO_DEPTH_Pos 3
#define PS2_PS2CON_TXFIFO_DEPTH_Msk (0xFul << PS2_PS2CON_TXFIFO_DEPTH_Pos)
#define PS2_PS2CON_ACK_Pos 7
#define PS2_PS2CON_ACK_Msk (1ul << PS2_PS2CON_ACK_Pos)
#define PS2_PS2CON_CLRFIFO_Pos 8
#define PS2_PS2CON_CLRFIFO_Msk (1ul << PS2_PS2CON_CLRFIFO_Pos)
#define PS2_PS2CON_OVERRIDE_Pos 9
#define PS2_PS2CON_OVERRIDE_Msk (1ul << PS2_PS2CON_OVERRIDE_Pos)
#define PS2_PS2CON_FPS2CLK_Pos 10
#define PS2_PS2CON_FPS2CLK_Msk (1ul << PS2_PS2CON_FPS2CLK_Pos)
#define PS2_PS2CON_FPS2DAT_Pos 11
#define PS2_PS2CON_FPS2DAT_Msk (1ul << PS2_PS2CON_FPS2DAT_Pos)
/* PS/2 PS2RXDATA Bit Field Definitions */
#define PS2_PS2RXDATA_RXDATA_Pos 0
#define PS2_PS2RXDATA_RXDATA_Msk (0xFFul << PS2_PS2RXDATA_RXDATA_Pos)
/* PS/2 PS2STATUS Bit Field Definitions */
#define PS2_PS2STATUS_PS2CLK_Pos 0
#define PS2_PS2STATUS_PS2CLK_Msk (1ul << PS2_PS2STATUS_PS2CLK_Pos)
#define PS2_PS2STATUS_PS2DATA_Pos 1
#define PS2_PS2STATUS_PS2DATA_Msk (1ul << PS2_PS2STATUS_PS2DATA_Pos)
#define PS2_PS2STATUS_FRAMERR_Pos 2
#define PS2_PS2STATUS_FRAMERR_Msk (1ul << PS2_PS2STATUS_FRAMERR_Pos)
#define PS2_PS2STATUS_RXPARITY_Pos 3
#define PS2_PS2STATUS_RXPARITY_Msk (1ul << PS2_PS2STATUS_RXPARITY_Pos)
#define PS2_PS2STATUS_RXPARITY_Pos 3
#define PS2_PS2STATUS_RXPARITY_Msk (1ul << PS2_PS2STATUS_RXPARITY_Pos)
#define PS2_PS2STATUS_RXBUSY_Pos 4
#define PS2_PS2STATUS_RXBUSY_Msk (1ul << PS2_PS2STATUS_RXBUSY_Pos)
#define PS2_PS2STATUS_TXBUSY_Pos 5
#define PS2_PS2STATUS_TXBUSY_Msk (1ul << PS2_PS2STATUS_TXBUSY_Pos)
#define PS2_PS2STATUS_RXOVF_Pos 6
#define PS2_PS2STATUS_RXOVF_Msk (1ul << PS2_PS2STATUS_RXOVF_Pos)
#define PS2_PS2STATUS_TXEMPTY_Pos 7
#define PS2_PS2STATUS_TXEMPTY_Msk (1ul << PS2_PS2STATUS_TXEMPTY_Pos)
#define PS2_PS2STATUS_BYTEIDX_Pos 8
#define PS2_PS2STATUS_BYTEIDX_Msk (0xFul << PS2_PS2STATUS_BYTEIDX_Pos)
/* PS/2 PS2INTID Bit Field Definitions */
#define PS2_PS2INTID_RXINT_Pos 0
#define PS2_PS2INTID_RXINT_Msk (1ul << PS2_PS2INTID_RXINT_Pos)
#define PS2_PS2INTID_TXINT_Pos 1
#define PS2_PS2INTID_TXINT_Msk (1ul << PS2_PS2INTID_TXINT_Pos)
/*--------------------------- USB Device Controller --------------------------*/
typedef struct
{
__IO uint32_t BUS_IE:1;
__IO uint32_t USB_IE:1;
__IO uint32_t FLDET_IE:1;
__IO uint32_t WAKEUP_IE:1;
__I uint32_t RESERVE0:4;
__IO uint32_t WAKEUP_EN:1;
__I uint32_t RESERVE1:6;
__IO uint32_t INNAK_EN:1;
__I uint32_t RESERVE2:16;
} USBD_INTEN_T;
typedef struct
{
__IO uint32_t BUS_STS:1;
__IO uint32_t USB_STS:1;
__IO uint32_t FLDET_STS:1;
__IO uint32_t WAKEUP_STS:1;
__I uint32_t RESERVE0:12;
__IO uint32_t EPEVT:6;
__I uint32_t RESERVE1:9;
__IO uint32_t SETUP:1;
} USBD_INTSTS_T;
typedef struct
{
__IO uint32_t FADDR:7;
__I uint32_t RESERVE:25;
} USBD_FADDR_T;
typedef struct
{
__I uint32_t RESERVE0:7;
__I uint32_t OVERRUN:1;
__I uint32_t EPSTS0:3;
__I uint32_t EPSTS1:3;
__I uint32_t EPSTS2:3;
__I uint32_t EPSTS3:3;
__I uint32_t EPSTS4:3;
__I uint32_t EPSTS5:3;
__I uint32_t RESERVE1:6;
} USBD_EPSTS_T;
typedef struct
{
__I uint32_t USBRST:1;
__I uint32_t SUSPEND:1;
__I uint32_t RESUME:1;
__I uint32_t TIMEOUT:1;
__IO uint32_t PHY_EN:1;
__IO uint32_t RWAKEUP:1;
__I uint32_t RESERVE0:1;
__IO uint32_t USB_EN:1;
__IO uint32_t DPPU_EN:1;
__IO uint32_t PWRDN:1;
__I uint32_t RESERVE1:22;
} USBD_ATTR_T;
typedef struct
{
__IO uint32_t FLDET:1;
__I uint32_t RESERVE:31;
} USBD_FLDET_T;
typedef struct
{
__I uint32_t RESERVE0:3;
__IO uint32_t STBUFSEG:6;
__I uint32_t RESERVE:23;
} USBD_STBUFSEG_T;
typedef struct
{
__IO uint32_t MXPLD:9;
__I uint32_t RESERVE:23;
} USBD_MXPLD_T;
typedef struct
{
__IO uint32_t EP_NUM:4;
__IO uint32_t ISOCH:1;
__IO uint32_t STATE:2;
__IO uint32_t DSQ_SYNC:1;
__I uint32_t RESERVE0:1;
__IO uint32_t CSTALL:1;
__I uint32_t RESERVE1:22;
} USBD_CFG_T;
typedef struct
{
__IO uint32_t CLRRDY:1;
__IO uint32_t SSTALL:1;
__I uint32_t RESERVE:30;
} USBD_CFGP_T;
typedef struct
{
__IO uint32_t DRVSE0:1;
__I uint32_t RESERVE:31;
} USBD_DRVSE0_T;
typedef struct
{
union {
__IO uint32_t u32BUFSEG;
struct {
__I uint32_t RESERVE0:3;
__IO uint32_t BUFSEG:6;
__I uint32_t RESERVE:23;
} BUFSEG;
};
union {
__IO uint32_t u32MXPLD;
struct {
__IO uint32_t MXPLD:9;
__I uint32_t RESERVE:23;
} MXPLD;
};
union {
__IO uint32_t u32CFG;
struct {
__IO uint32_t EP_NUM:4;
__IO uint32_t ISOCH:1;
__IO uint32_t STATE:2;
__IO uint32_t DSQ_SYNC:1;
__I uint32_t RESERVE0:1;
__IO uint32_t CSTALL:1;
__I uint32_t RESERVE1:22;
} CFG;
};
union {
__IO uint32_t u32CFGP;
struct {
__IO uint32_t CLRRDY:1;
__IO uint32_t SSTALL:1;
__I uint32_t RESERVE:30;
} CFGP;
};
} USBD_EP_T;
typedef struct
{
union {
__IO uint32_t u32INTEN;
struct {
__IO uint32_t BUS_IE:1;
__IO uint32_t USB_IE:1;
__IO uint32_t FLDET_IE:1;
__IO uint32_t WAKEUP_IE:1;
__I uint32_t RESERVE0:4;
__IO uint32_t WAKEUP_EN:1;
__I uint32_t RESERVE1:6;
__IO uint32_t INNAK_EN:1;
__I uint32_t RESERVE2:16;
} INTEN;
};
union {
__IO uint32_t u32INTSTS;
struct {
__IO uint32_t BUS_STS:1;
__IO uint32_t USB_STS:1;
__IO uint32_t FLDET_STS:1;
__IO uint32_t WAKEUP_STS:1;
__I uint32_t RESERVE0:12;
__IO uint32_t EPEVT:6;
__I uint32_t RESERVE1:9;
__IO uint32_t SETUP:1;
} INTSTS;
};
union {
__IO uint32_t u32FADDR;
struct {
__IO uint32_t FADDR:7;
__I uint32_t RESERVE:25;
} FADDR;
};
union {
__IO uint32_t u32EPSTS;
struct {
__I uint32_t RESERVE0:7;
__I uint32_t OVERRUN:1;
__I uint32_t EPSTS0:3;
__I uint32_t EPSTS1:3;
__I uint32_t EPSTS2:3;
__I uint32_t EPSTS3:3;
__I uint32_t EPSTS4:3;
__I uint32_t EPSTS5:3;
__I uint32_t RESERVE1:6;
} EPSTS;
};
union {
__IO uint32_t u32ATTR;
struct {
__I uint32_t USBRST:1;
__I uint32_t SUSPEND:1;
__I uint32_t RESUME:1;
__I uint32_t TIMEOUT:1;
__IO uint32_t PHY_EN:1;
__IO uint32_t RWAKEUP:1;
__I uint32_t RESERVE0:1;
__IO uint32_t USB_EN:1;
__IO uint32_t DPPU_EN:1;
__IO uint32_t PWRDN:1;
__I uint32_t RESERVE1:22;
} ATTR;
};
union {
__IO uint32_t u32FLDET;
struct {
__I uint32_t FLDET:1;
__I uint32_t RESERVE:31;
} FLDET;
};
union {
__IO uint32_t u32STBUFSEG;
struct {
__I uint32_t RESERVE0:3;
__IO uint32_t STBUFSEG:6;
__I uint32_t RESERVE:23;
} STBUFSEG;
};
__I uint32_t RESERVE0;
USBD_EP_T EP[6];
__I uint32_t RESERVE1[4];
union {
__IO uint32_t u32DRVSE0;
struct {
__IO uint32_t DRVSE0:1;
__I uint32_t RESERVE:31;
} DRVSE0;
};
__I uint32_t RESERVE2[4];
} USBD_T;
/* USBD INTEN Bit Field Definitions */
#define USBD_INTEN_INNAK_EN_Pos 15
#define USBD_INTEN_INNAK_EN_Msk (1ul << USBD_INTEN_INNAK_EN_Pos)
#define USBD_INTEN_WAKEUP_EN_Pos 8
#define USBD_INTEN_WAKEUP_EN_Msk (1ul << USBD_INTEN_WAKEUP_EN_Pos)
#define USBD_INTEN_WAKEUP_IE_Pos 3
#define USBD_INTEN_WAKEUP_IE_Msk (1ul << USBD_INTEN_WAKEUP_IE_Pos)
#define USBD_INTEN_FLDET_IE_Pos 2
#define USBD_INTEN_FLDET_IE_Msk (1ul << USBD_INTEN_FLDET_IE_Pos)
#define USBD_INTEN_USB_IE_Pos 1
#define USBD_INTEN_USB_IE_Msk (1ul << USBD_INTEN_USB_IE_Pos)
#define USBD_INTEN_BUS_IE_Pos 0
#define USBD_INTEN_BUS_IE_Msk (1ul << USBD_INTEN_BUS_IE_Pos)
/* USBD INTSTS Bit Field Definitions */
#define USBD_INTSTS_SETUP_Pos 31
#define USBD_INTSTS_SETUP_Msk (1ul << USBD_INTSTS_SETUP_Pos)
#define USBD_INTSTS_EPEVT_Pos 16
#define USBD_INTSTS_EPEVT_Msk (0x3Ful << USBD_INTSTS_EPEVT_Pos)
#define USBD_INTSTS_WAKEUP_STS_Pos 3
#define USBD_INTSTS_WAKEUP_STS_Msk (1ul << USBD_INTSTS_WAKEUP_STS_Pos)
#define USBD_INTSTS_FLDET_STS_Pos 2
#define USBD_INTSTS_FLDET_STS_Msk (1ul << USBD_INTSTS_FLDET_STS_Pos)
#define USBD_INTSTS_USB_STS_Pos 1
#define USBD_INTSTS_USB_STS_Msk (1ul << USBD_INTSTS_USB_STS_Pos)
#define USBD_INTSTS_BUS_STS_Pos 0
#define USBD_INTSTS_BUS_STS_Msk (1ul << USBD_INTSTS_BUS_STS_Pos)
/* USBD FADDR Bit Field Definitions */
#define USBD_FADDR_FADDR_Pos 0
#define USBD_FADDR_FADDR_Msk (0x7Ful << USBD_FADDR_FADDR_Pos)
/* USBD EPSTS Bit Field Definitions */
#define USBD_EPSTS_EPSTS5_Pos 23
#define USBD_EPSTS_EPSTS5_Msk (7ul << USBD_EPSTS_EPSTS5_Pos)
#define USBD_EPSTS_EPSTS4_Pos 20
#define USBD_EPSTS_EPSTS4_Msk (7ul << USBD_EPSTS_EPSTS4_Pos)
#define USBD_EPSTS_EPSTS3_Pos 17
#define USBD_EPSTS_EPSTS3_Msk (7ul << USBD_EPSTS_EPSTS3_Pos)
#define USBD_EPSTS_EPSTS2_Pos 14
#define USBD_EPSTS_EPSTS2_Msk (7ul << USBD_EPSTS_EPSTS2_Pos)
#define USBD_EPSTS_EPSTS1_Pos 11
#define USBD_EPSTS_EPSTS1_Msk (7ul << USBD_EPSTS_EPSTS1_Pos)
#define USBD_EPSTS_EPSTS0_Pos 8
#define USBD_EPSTS_EPSTS0_Msk (7ul << USBD_EPSTS_EPSTS0_Pos)
#define USBD_EPSTS_OVERRUN_Pos 7
#define USBD_EPSTS_OVERRUN_Msk (1ul << USBD_EPSTS_OVERRUN_Pos)
/* USBD ATTR Bit Field Definitions */
#define USBD_ATTR_PWRDN_Pos 9
#define USBD_ATTR_PWRDN_Msk (1ul << USBD_ATTR_PWRDN_Pos)
#define USBD_ATTR_DPPU_EN_Pos 8
#define USBD_ATTR_DPPU_EN_Msk (1ul << USBD_ATTR_DPPU_EN_Pos)
#define USBD_ATTR_USB_EN_Pos 7
#define USBD_ATTR_USB_EN_Msk (1ul << USBD_ATTR_USB_EN_Pos)
#define USBD_ATTR_RWAKEUP_Pos 5
#define USBD_ATTR_RWAKEUP_Msk (1ul << USBD_ATTR_RWAKEUP_Pos)
#define USBD_ATTR_PHY_EN_Pos 4
#define USBD_ATTR_PHY_EN_Msk (1ul << USBD_ATTR_PHY_EN_Pos)
#define USBD_ATTR_TIMEOUT_Pos 3
#define USBD_ATTR_TIMEOUT_Msk (1ul << USBD_ATTR_TIMEOUT_Pos)
#define USBD_ATTR_RESUME_Pos 2
#define USBD_ATTR_RESUME_Msk (1ul << USBD_ATTR_RESUME_Pos)
#define USBD_ATTR_SUSPEND_Pos 1
#define USBD_ATTR_SUSPEND_Msk (1ul << USBD_ATTR_SUSPEND_Pos)
#define USBD_ATTR_USBRST_Pos 0
#define USBD_ATTR_USBRST_Msk (1ul << USBD_ATTR_USBRST_Pos)
/* USBD FLDET Bit Field Definitions */
#define USBD_FLDET_FLDET_Pos 0
#define USBD_FLDET_FLDET_Msk (1ul << USBD_FLDET_FLDET_Pos)
/* USBD STBUFSEG Bit Field Definitions */
#define USBD_STBUFSEG_STBUFSEG_Pos 3
#define USBD_STBUFSEG_STBUFSEG_Msk (0x3Ful << USBD_STBUFSEG_STBUFSEG_Pos)
/* USBD BUFSEG Bit Field Definitions */
#define USBD_BUFSEG_BUFSEG_Pos 3
#define USBD_BUFSEG_BUFSEG_Msk (0x3Ful << USBD_BUFSEG_BUFSEG_Pos)
/* USBD MXPLD Bit Field Definitions */
#define USBD_MXPLD_MXPLD_Pos 0
#define USBD_MXPLD_MXPLD_Msk (0x1FFul << USBD_MXPLD_MXPLD_Pos)
/* USBD CFG Bit Field Definitions */
#define USBD_CFG_CSTALL_Pos 9
#define USBD_CFG_CSTALL_Msk (1ul << USBD_CFG_CSTALL_Pos)
#define USBD_CFG_DSQ_SYNC_Pos 7
#define USBD_CFG_DSQ_SYNC_Msk (1ul << USBD_CFG_DSQ_SYNC_Pos)
#define USBD_CFG_STATE_Pos 5
#define USBD_CFG_STATE_Msk (3ul << USBD_CFG_STATE_Pos)
#define USBD_CFG_ISOCH_Pos 4
#define USBD_CFG_ISOCH_Msk (1ul << USBD_CFG_ISOCH_Pos)
#define USBD_CFG_EP_NUM_Pos 0
#define USBD_CFG_EP_NUM_Msk (0xFul << USBD_CFG_EP_NUM_Pos)
/* USBD CFGP Bit Field Definitions */
#define USBD_CFGP_SSTALL_Pos 1
#define USBD_CFGP_SSTALL_Msk (1ul << USBD_CFGP_SSTALL_Pos)
#define USBD_CFGP_CLRRDY_Pos 0
#define USBD_CFGP_CLRRDY_Msk (1ul << USBD_CFGP_CLRRDY_Pos)
/* USBD DRVSE0 Bit Field Definitions */
#define USBD_DRVSE0_DRVSE0_Pos 0
#define USBD_DRVSE0_DRVSE0_Msk (1ul << USBD_DRVSE0_DRVSE0_Pos)
/*----------------------------- PWM Controller -------------------------------*/
typedef struct
{
__IO uint32_t CP01:8;
__IO uint32_t CP23:8;
__IO uint32_t DZI01:8;
__IO uint32_t DZI23:8;
} PWM_PPR_T;
typedef struct
{
__IO uint32_t CSR0:3;
__I uint32_t RESERVE0:1;
__IO uint32_t CSR1:3;
__I uint32_t RESERVE1:1;
__IO uint32_t CSR2:3;
__I uint32_t RESERVE2:1;
__IO uint32_t CSR3:3;
__I uint32_t RESERVE3:17;
} PWM_CSR_T;
typedef struct
{
__IO uint32_t CH0EN:1;
__I uint32_t RESERVE0:1;
__IO uint32_t CH0INV:1;
__IO uint32_t CH0MOD:1;
__IO uint32_t DZEN01:1;
__IO uint32_t DZEN23:1;
__I uint32_t RESERVE1:2;
__IO uint32_t CH1EN:1;
__I uint32_t RESERVE2:1;
__IO uint32_t CH1INV:1;
__IO uint32_t CH1MOD:1;
__I uint32_t RESERVE3:4;
__IO uint32_t CH2EN:1;
__I uint32_t RESERVE4:1;
__IO uint32_t CH2INV:1;
__IO uint32_t CH2MOD:1;
__I uint32_t RESERVE5:4;
__IO uint32_t CH3EN:1;
__I uint32_t RESERVE6:1;
__IO uint32_t CH3INV:1;
__IO uint32_t CH3MOD:1;
__I uint32_t RESERVE7:4;
} PWM_PCR_T;
typedef __IO uint32_t PWM_CNR_T;
typedef __IO uint32_t PWM_CMR_T;
typedef __I uint32_t PWM_PDR_T;
typedef struct
{
__IO uint32_t PWMIE0:1;
__IO uint32_t PWMIE1:1;
__IO uint32_t PWMIE2:1;
__IO uint32_t PWMIE3:1;
__I uint32_t RESERVE:28;
} PWM_PIER_T;
typedef struct
{
__IO uint32_t PWMIF0:1;
__IO uint32_t PWMIF1:1;
__IO uint32_t PWMIF2:1;
__IO uint32_t PWMIF3:1;
__I uint32_t RESERVE:28;
} PWM_PIIR_T;
typedef struct
{
__IO uint32_t INV0:1;
__IO uint32_t CRL_IE0:1;
__IO uint32_t CFL_IE0:1;
__IO uint32_t CAPCH0EN:1;
__IO uint32_t CAPIF0:1;
__I uint32_t RESERVE0:1;
__IO uint32_t CRLRI0:1;
__IO uint32_t CFLRI0:1;
__I uint32_t RESERVE1:8;
__IO uint32_t INV1:1;
__IO uint32_t CRL_IE1:1;
__IO uint32_t CFL_IE1:1;
__IO uint32_t CAPCH1EN:1;
__IO uint32_t CAPIF1:1;
__I uint32_t RESERVE2:1;
__IO uint32_t CRLRI1:1;
__IO uint32_t CFLRI1:1;
__I uint32_t RESERVE3:8;
} PWM_CCR0_T;
typedef struct
{
__IO uint32_t INV2:1;
__IO uint32_t CRL_IE2:1;
__IO uint32_t CFL_IE2:1;
__IO uint32_t CAPCH2EN:1;
__IO uint32_t CAPIF2:1;
__I uint32_t RESERVE0:1;
__IO uint32_t CRLRI2:1;
__IO uint32_t CFLRI2:1;
__I uint32_t RESERVE1:8;
__IO uint32_t INV3:1;
__IO uint32_t CRL_IE3:1;
__IO uint32_t CFL_IE3:1;
__IO uint32_t CAPCH3EN:1;
__IO uint32_t CAPIF3:1;
__I uint32_t RESERVE2:1;
__IO uint32_t CRLRI3:1;
__IO uint32_t CFLRI3:1;
__I uint32_t RESERVE3:8;
} PWM_CCR2_T;
typedef __IO uint32_t PWM_CRLR_T;
typedef __IO uint32_t PWM_CFLR_T;
typedef __IO uint32_t PWM_CAPENR_T;
typedef struct
{
__IO uint32_t PWM0:1;
__IO uint32_t PWM1:1;
__IO uint32_t PWM2:1;
__IO uint32_t PWM3:1;
__I uint32_t RESERVE:28;
} PWM_POE_T;
typedef struct
{
union
{
__IO uint32_t u32PPR;
struct
{
__IO uint32_t CP01:8;
__IO uint32_t CP23:8;
__IO uint32_t DZI01:8;
__IO uint32_t DZI23:8;
} PPR;
};
union
{
__IO uint32_t u32CSR;
struct
{
__IO uint32_t CSR0:3;
__I uint32_t RESERVE0:1;
__IO uint32_t CSR1:3;
__I uint32_t RESERVE1:1;
__IO uint32_t CSR2:3;
__I uint32_t RESERVE2:1;
__IO uint32_t CSR3:3;
__I uint32_t RESERVE3:17;
} CSR;
};
union
{
__IO uint32_t u32PCR;
struct
{
__IO uint32_t CH0EN:1;
__I uint32_t RESERVE0:1;
__IO uint32_t CH0INV:1;
__IO uint32_t CH0MOD:1;
__IO uint32_t DZEN01:1;
__IO uint32_t DZEN23:1;
__I uint32_t RESERVE1:2;
__IO uint32_t CH1EN:1;
__I uint32_t RESERVE2:1;
__IO uint32_t CH1INV:1;
__IO uint32_t CH1MOD:1;
__I uint32_t RESERVE3:4;
__IO uint32_t CH2EN:1;
__I uint32_t RESERVE4:1;
__IO uint32_t CH2INV:1;
__IO uint32_t CH2MOD:1;
__I uint32_t RESERVE5:4;
__IO uint32_t CH3EN:1;
__I uint32_t RESERVE6:1;
__IO uint32_t CH3INV:1;
__IO uint32_t CH3MOD:1;
__I uint32_t RESERVE7:4;
} PCR;
};
union
{
__IO uint32_t u32CNR0;
__IO uint32_t CNR0;
};
union
{
__IO uint32_t u32CMR0;
__IO uint32_t CMR0;
};
union
{
__I uint32_t u32PDR0;
__I uint32_t PDR0;
};
union
{
__IO uint32_t u32CNR1;
__IO uint32_t CNR1;
};
union
{
__IO uint32_t u32CMR1;
__IO uint32_t CMR1;
};
union
{
__I uint32_t u32PDR1;
__I uint32_t PDR1;
};
union
{
__IO uint32_t u32CNR2;
__IO uint32_t CNR2;
};
union
{
__IO uint32_t u32CMR2;
__IO uint32_t CMR2;
};
union
{
__I uint32_t u32PDR2;
__I uint32_t PDR2;
};
union
{
__IO uint32_t u32CNR3;
__IO uint32_t CNR3;
};
union
{
__IO uint32_t u32CMR3;
__IO uint32_t CMR3;
};
union
{
__I uint32_t u32PDR3;
__I uint32_t PDR3;
};
__I uint32_t RESERVE0;
union
{
__IO uint32_t u32PIER;
struct
{
__IO uint32_t PWMIE0:1;
__IO uint32_t PWMIE1:1;
__IO uint32_t PWMIE2:1;
__IO uint32_t PWMIE3:1;
__I uint32_t RESERVE:28;
} PIER;
};
union
{
__IO uint32_t u32PIIR;
struct
{
__IO uint32_t PWMIF0:1;
__IO uint32_t PWMIF1:1;
__IO uint32_t PWMIF2:1;
__IO uint32_t PWMIF3:1;
__I uint32_t RESERVE:28;
} PIIR;
};
__I uint32_t RESERVE1[2];
union
{
__IO uint32_t u32CCR0;
struct
{
__IO uint32_t INV0:1;
__IO uint32_t CRL_IE0:1;
__IO uint32_t CFL_IE0:1;
__IO uint32_t CAPCH0EN:1;
__IO uint32_t CAPIF0:1;
__I uint32_t RESERVE0:1;
__IO uint32_t CRLRI0:1;
__IO uint32_t CFLRI0:1;
__I uint32_t RESERVE1:8;
__IO uint32_t INV1:1;
__IO uint32_t CRL_IE1:1;
__IO uint32_t CFL_IE1:1;
__IO uint32_t CAPCH1EN:1;
__IO uint32_t CAPIF1:1;
__I uint32_t RESERVE2:1;
__IO uint32_t CRLRI1:1;
__IO uint32_t CFLRI1:1;
__I uint32_t RESERVE3:8;
} CCR0;
};
union
{
__IO uint32_t u32CCR2;
struct
{
__IO uint32_t INV2:1;
__IO uint32_t CRL_IE2:1;
__IO uint32_t CFL_IE2:1;
__IO uint32_t CAPCH2EN:1;
__IO uint32_t CAPIF2:1;
__I uint32_t RESERVE0:1;
__IO uint32_t CRLRI2:1;
__IO uint32_t CFLRI2:1;
__I uint32_t RESERVE1:8;
__IO uint32_t INV3:1;
__IO uint32_t CRL_IE3:1;
__IO uint32_t CFL_IE3:1;
__IO uint32_t CAPCH3EN:1;
__IO uint32_t CAPIF3:1;
__I uint32_t RESERVE2:1;
__IO uint32_t CRLRI3:1;
__IO uint32_t CFLRI3:1;
__I uint32_t RESERVE3:8;
} CCR2;
};
union
{
__IO uint32_t u32CRLR0;
__IO uint32_t CRLR0;
};
union
{
__IO uint32_t u32CFLR0;
__IO uint32_t CFLR0;
};
union
{
__IO uint32_t u32CRLR1;
__IO uint32_t CRLR1;
};
union
{
__IO uint32_t u32CFLR1;
__IO uint32_t CFLR1;
};
union
{
__IO uint32_t u32CRLR2;
__IO uint32_t CRLR2;
};
union
{
__IO uint32_t u32CFLR2;
__IO uint32_t CFLR2;
};
union
{
__IO uint32_t u32CRLR3;
__IO uint32_t CRLR3;
};
union
{
__IO uint32_t u32CFLR3;
__IO uint32_t CFLR3;
};
union
{
__IO uint32_t u32CAPENR;
__IO uint32_t CAPENR;
};
union
{
__IO uint32_t u32POE;
struct
{
__IO uint32_t PWM0:1;
__IO uint32_t PWM1:1;
__IO uint32_t PWM2:1;
__IO uint32_t PWM3:1;
__I uint32_t RESERVE:28;
} POE;
};
} PWM_T;
/* PWM PPR Bit Field Definitions */
#define PWM_PPR_DZI23_Pos 24
#define PWM_PPR_DZI23_Msk (0xFFul << PWM_PPR_DZI23_Pos)
#define PWM_PPR_DZI01_Pos 16
#define PWM_PPR_DZI01_Msk (0xFFul << PWM_PPR_DZI01_Pos)
#define PWM_PPR_CP23_Pos 8
#define PWM_PPR_CP23_Msk (0xFFul << PWM_PPR_CP23_Pos)
#define PWM_PPR_CP01_Pos 0
#define PWM_PPR_CP01_Msk (0xFFul << PWM_PPR_CP01_Pos)
/* PWM CSR Bit Field Definitions */
#define PWM_CSR_CSR3_Pos 12
#define PWM_CSR_CSR3_Msk (7ul << PWM_CSR_CSR3_Pos)
#define PWM_CSR_CSR2_Pos 8
#define PWM_CSR_CSR2_Msk (7ul << PWM_CSR_CSR2_Pos)
#define PWM_CSR_CSR1_Pos 4
#define PWM_CSR_CSR1_Msk (7ul << PWM_CSR_CSR1_Pos)
#define PWM_CSR_CSR0_Pos 0
#define PWM_CSR_CSR0_Msk (7ul << PWM_CSR_CSR0_Pos)
/* PWM PCR Bit Field Definitions */
#define PWM_PCR_CH3MOD_Pos 27
#define PWM_PCR_CH3MOD_Msk (1ul << PWM_PCR_CH3MOD_Pos)
#define PWM_PCR_CH3INV_Pos 26
#define PWM_PCR_CH3INV_Msk (1ul << PWM_PCR_CH3INV_Pos)
#define PWM_PCR_CH3EN_Pos 24
#define PWM_PCR_CH3EN_Msk (1ul << PWM_PCR_CH3EN_Pos)
#define PWM_PCR_CH2MOD_Pos 19
#define PWM_PCR_CH2MOD_Msk (1ul << PWM_PCR_CH2MOD_Pos)
#define PWM_PCR_CH2INV_Pos 18
#define PWM_PCR_CH2INV_Msk (1ul << PWM_PCR_CH2INV_Pos)
#define PWM_PCR_CH2EN_Pos 16
#define PWM_PCR_CH2EN_Msk (1ul << PWM_PCR_CH2EN_Pos)
#define PWM_PCR_CH1MOD_Pos 11
#define PWM_PCR_CH1MOD_Msk (1ul << PWM_PCR_CH1MOD_Pos)
#define PWM_PCR_CH1INV_Pos 10
#define PWM_PCR_CH1INV_Msk (1ul << PWM_PCR_CH1INV_Pos)
#define PWM_PCR_CH1EN_Pos 8
#define PWM_PCR_CH1EN_Msk (1ul << PWM_PCR_CH1EN_Pos)
#define PWM_PCR_DZEN23_Pos 5
#define PWM_PCR_DZEN23_Msk (1ul << PWM_PCR_DZEN23_Pos)
#define PWM_PCR_DZEN01_Pos 4
#define PWM_PCR_DZEN01_Msk (1ul << PWM_PCR_DZEN01_Pos)
#define PWM_PCR_CH0MOD_Pos 3
#define PWM_PCR_CH0MOD_Msk (1ul << PWM_PCR_CH0MOD_Pos)
#define PWM_PCR_CH0INV_Pos 2
#define PWM_PCR_CH0INV_Msk (1ul << PWM_PCR_CH0INV_Pos)
#define PWM_PCR_CH0EN_Pos 0
#define PWM_PCR_CH0EN_Msk (1ul << PWM_PCR_CH0EN_Pos)
/* PWM CNR Bit Field Definitions */
#define PWM_CNR_CNR_Pos 0
#define PWM_CNR_CNR_Msk (0xFFFFul << PWM_CNR_CNR_Pos)
/* PWM CMR Bit Field Definitions */
#define PWM_CMR_CMR_Pos 0
#define PWM_CMR_CMR_Msk (0xFFFFul << PWM_CMR_CMR_Pos)
/* PWM PDR Bit Field Definitions */
#define PWM_PDR_PDR_Pos 0
#define PWM_PDR_PDR_Msk (0xFFFFul << PWM_PDR_PDR_Pos)
/* PWM PIER Bit Field Definitions */
#define PWM_PIER_PWMIE3_Pos 3
#define PWM_PIER_PWMIE3_Msk (1ul << PWM_PIER_PWMIE3_Pos)
#define PWM_PIER_PWMIE2_Pos 2
#define PWM_PIER_PWMIE2_Msk (1ul << PWM_PIER_PWMIE2_Pos)
#define PWM_PIER_PWMIE1_Pos 1
#define PWM_PIER_PWMIE1_Msk (1ul << PWM_PIER_PWMIE1_Pos)
#define PWM_PIER_PWMIE0_Pos 0
#define PWM_PIER_PWMIE0_Msk (1ul << PWM_PIER_PWMIE0_Pos)
/* PWM PIIR Bit Field Definitions */
#define PWM_PIIR_PWMIF3_Pos 3
#define PWM_PIIR_PWMIF3_Msk (1ul << PWM_PIIR_PWMIF3_Pos)
#define PWM_PIIR_PWMIF2_Pos 2
#define PWM_PIIR_PWMIF2_Msk (1ul << PWM_PIIR_PWMIF2_Pos)
#define PWM_PIIR_PWMIF1_Pos 1
#define PWM_PIIR_PWMIF1_Msk (1ul << PWM_PIIR_PWMIF1_Pos)
#define PWM_PIIR_PWMIF0_Pos 0
#define PWM_PIIR_PWMIF0_Msk (1ul << PWM_PIIR_PWMIF0_Pos)
/* PWM CCR0 Bit Field Definitions */
#define PWM_CCR0_CFLRI1_Pos 23
#define PWM_CCR0_CFLRI1_Msk (1ul << PWM_CCR0_CFLRI1_Pos)
#define PWM_CCR0_CRLRI1_Pos 22
#define PWM_CCR0_CRLRI1_Msk (1ul << PWM_CCR0_CRLRI1_Pos)
#define PWM_CCR0_CAPIF1_Pos 20
#define PWM_CCR0_CAPIF1_Msk (1ul << PWM_CCR0_CAPIF1_Pos)
#define PWM_CCR0_CAPCH1EN_Pos 19
#define PWM_CCR0_CAPCH1EN_Msk (1ul << PWM_CCR0_CAPCH1EN_Pos)
#define PWM_CCR0_CFL_IE1_Pos 18
#define PWM_CCR0_CFL_IE1_Msk (1ul << PWM_CCR0_CFL_IE1_Pos)
#define PWM_CCR0_CRL_IE1_Pos 17
#define PWM_CCR0_CRL_IE1_Msk (1ul << PWM_CCR0_CRL_IE1_Pos)
#define PWM_CCR0_INV1_Pos 16
#define PWM_CCR0_INV1_Msk (1ul << PWM_CCR0_INV1_Pos)
#define PWM_CCR0_CFLRI0_Pos 7
#define PWM_CCR0_CFLRI0_Msk (1ul << PWM_CCR0_CFLRI0_Pos)
#define PWM_CCR0_CRLRI0_Pos 6
#define PWM_CCR0_CRLRI0_Msk (1ul << PWM_CCR0_CRLRI0_Pos)
#define PWM_CCR0_CAPIF0_Pos 4
#define PWM_CCR0_CAPIF0_Msk (1ul << PWM_CCR0_CAPIF0_Pos)
#define PWM_CCR0_CAPCH0EN_Pos 3
#define PWM_CCR0_CAPCH0EN_Msk (1ul << PWM_CCR0_CAPCH0EN_Pos)
#define PWM_CCR0_CFL_IE0_Pos 2
#define PWM_CCR0_CFL_IE0_Msk (1ul << PWM_CCR0_CFL_IE0_Pos)
#define PWM_CCR0_CRL_IE0_Pos 1
#define PWM_CCR0_CRL_IE0_Msk (1ul << PWM_CCR0_CRL_IE0_Pos)
#define PWM_CCR0_INV0_Pos 0
#define PWM_CCR0_INV0_Msk (1ul << PWM_CCR0_INV0_Pos)
/* PWM CCR2 Bit Field Definitions */
#define PWM_CCR2_CFLRI3_Pos 23
#define PWM_CCR2_CFLRI3_Msk (1ul << PWM_CCR2_CFLRI3_Pos)
#define PWM_CCR2_CRLRI3_Pos 22
#define PWM_CCR2_CRLRI3_Msk (1ul << PWM_CCR2_CRLRI3_Pos)
#define PWM_CCR2_CAPIF3_Pos 20
#define PWM_CCR2_CAPIF3_Msk (1ul << PWM_CCR2_CAPIF3_Pos)
#define PWM_CCR2_CAPCH3EN_Pos 19
#define PWM_CCR2_CAPCH3EN_Msk (1ul << PWM_CCR2_CAPCH3EN_Pos)
#define PWM_CCR2_CFL_IE3_Pos 18
#define PWM_CCR2_CFL_IE3_Msk (1ul << PWM_CCR2_CFL_IE3_Pos)
#define PWM_CCR2_CRL_IE3_Pos 17
#define PWM_CCR2_CRL_IE3_Msk (1ul << PWM_CCR2_CRL_IE3_Pos)
#define PWM_CCR2_INV3_Pos 16
#define PWM_CCR2_INV3_Msk (1ul << PWM_CCR2_INV3_Pos)
#define PWM_CCR2_CFLRI2_Pos 7
#define PWM_CCR2_CFLRI2_Msk (1ul << PWM_CCR2_CFLRI2_Pos)
#define PWM_CCR2_CRLRI2_Pos 6
#define PWM_CCR2_CRLRI2_Msk (1ul << PWM_CCR2_CRLRI2_Pos)
#define PWM_CCR2_CAPIF2_Pos 4
#define PWM_CCR2_CAPIF2_Msk (1ul << PWM_CCR2_CAPIF2_Pos)
#define PWM_CCR2_CAPCH2EN_Pos 3
#define PWM_CCR2_CAPCH2EN_Msk (1ul << PWM_CCR2_CAPCH2EN_Pos)
#define PWM_CCR2_CFL_IE2_Pos 2
#define PWM_CCR2_CFL_IE2_Msk (1ul << PWM_CCR2_CFL_IE2_Pos)
#define PWM_CCR2_CRL_IE2_Pos 1
#define PWM_CCR2_CRL_IE2_Msk (1ul << PWM_CCR2_CRL_IE2_Pos)
#define PWM_CCR2_INV2_Pos 0
#define PWM_CCR2_INV2_Msk (1ul << PWM_CCR2_INV2_Pos)
/* PWM CRLR Bit Field Definitions */
#define PWM_CRLR_CRLR_Pos 0
#define PWM_CRLR_CRLR_Msk (0xFFFFul << PWM_CRLR_CRLR_Pos)
/* PWM CFLR Bit Field Definitions */
#define PWM_CFLR_CFLR_Pos 0
#define PWM_CFLR_CFLR_Msk (0xFFFFul << PWM_CFLR_CFLR_Pos)
/* PWM CAPENR Bit Field Definitions */
#define PWM_CAPENR_CAPENR_Pos 0
#define PWM_CAPENR_CAPENR_Msk (0xFul << PWM_CAPENR_CAPENR_Pos)
/* PWM POE Bit Field Definitions */
#define PWM_POE_PWM3_Pos 3
#define PWM_POE_PWM3_Msk (1ul << PWM_POE_PWM3_Pos)
#define PWM_POE_PWM2_Pos 2
#define PWM_POE_PWM2_Msk (1ul << PWM_POE_PWM2_Pos)
#define PWM_POE_PWM1_Pos 1
#define PWM_POE_PWM1_Msk (1ul << PWM_POE_PWM1_Pos)
#define PWM_POE_PWM0_Pos 0
#define PWM_POE_PWM0_Msk (1ul << PWM_POE_PWM0_Pos)
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
/* Peripheral and SRAM base address */
#define FLASH_BASE (( uint32_t)0x00000000)
#define SRAM_BASE (( uint32_t)0x20000000)
#define AHB_BASE (( uint32_t)0x50000000)
#define APB1_BASE (( uint32_t)0x40000000)
#define APB2_BASE (( uint32_t)0x40100000)
/* Peripheral memory map */
#define GPIO_BASE (AHB_BASE + 0x4000)
#define GPIOA_BASE (GPIO_BASE )
#define GPIOB_BASE (GPIO_BASE + 0x0040)
#define GPIOC_BASE (GPIO_BASE + 0x0080)
#define GPIOD_BASE (GPIO_BASE + 0x00C0)
#define GPIO_DBNCECON_BASE (GPIO_BASE + 0x0180)
#define UART0_BASE (APB1_BASE + 0x50000)
#define UART1_BASE (APB2_BASE + 0x50000)
#define TIMER0_BASE (APB1_BASE + 0x10000)
#define TIMER1_BASE (APB1_BASE + 0x10020)
#define TIMER2_BASE (APB2_BASE + 0x10000)
#define TIMER3_BASE (APB2_BASE + 0x10020)
#define WDT_BASE (APB1_BASE + 0x4000)
#define SPI0_BASE (APB1_BASE + 0x30000)
#define SPI1_BASE (APB1_BASE + 0x34000)
#define I2C_BASE (APB2_BASE + 0x20000)
#define RTC_BASE (APB1_BASE + 0x08000)
#define SYSCLK_BASE (AHB_BASE + 0x00200)
#define GCR_BASE (AHB_BASE + 0x00000)
#define INT_BASE (AHB_BASE + 0x00300)
#define FMC_BASE (AHB_BASE + 0x0C000)
#define PS2_BASE (APB2_BASE + 0x00000)
#define USBD_BASE (APB1_BASE + 0x60000)
#define PWMA_BASE (APB1_BASE + 0x40000)
/******************************************************************************/
/* Peripheral declaration */
/******************************************************************************/
#define GPIOA ((GPIO_T *) GPIOA_BASE)
#define GPIOB ((GPIO_T *) GPIOB_BASE)
#define GPIOC ((GPIO_T *) GPIOC_BASE)
#define GPIOD ((GPIO_T *) GPIOD_BASE)
#define GPIO_DBNCECON ((GPIO_DBNCECON_T *) GPIO_DBNCECON_BASE)
#define GPIO_BIT_ADDR_BASE (GPIO_BASE + 0x200)
#define UART0 ((UART_T *) UART0_BASE)
#define UART1 ((UART_T *) UART1_BASE)
#define TIMER0 ((TIMER_T *) TIMER0_BASE)
#define TIMER1 ((TIMER_T *) TIMER1_BASE)
#define TIMER2 ((TIMER_T *) TIMER2_BASE)
#define TIMER3 ((TIMER_T *) TIMER3_BASE)
#define WDT ((WDT_T *) WDT_BASE)
#define SPI0 ((SPI_T *) SPI0_BASE)
#define SPI1 ((SPI_T *) SPI1_BASE)
#define I2C ((I2C_T *) I2C_BASE)
#define RTC ((RTC_T *) RTC_BASE)
#define SYSCLK ((SYSCLK_T *) SYSCLK_BASE)
#define SYS ((GCR_T *) GCR_BASE)
#define SYSINT ((GCR_INT_T *) INT_BASE)
#define FMC ((FMC_T *) FMC_BASE)
#define PS2 ((PS2_T *) PS2_BASE)
#define USBD ((USBD_T *) USBD_BASE)
#define PWMA ((PWM_T *) PWMA_BASE)
#define UNLOCKREG(x) *((__IO uint32_t *)(GCR_BASE + 0x100)) = 0x59;*((__IO uint32_t *)(GCR_BASE + 0x100)) = 0x16;*((__IO uint32_t *)(GCR_BASE + 0x100)) = 0x88
#define LOCKREG(x) *((__IO uint32_t *)(GCR_BASE + 0x100)) = 0x00;
#define REGCOPY(dest, src) *((uint32_t *)&(dest)) = *((uint32_t *)&(src))
#define CLEAR(dest) *((uint32_t *)&(dest)) = 0
//=============================================================================
typedef volatile unsigned char vu8;
typedef volatile unsigned long vu32;
typedef volatile unsigned short vu16;
#define M8(adr) (*((vu8 *) (adr)))
#define M16(adr) (*((vu16 *) (adr)))
#define M32(adr) (*((vu32 *) (adr)))
#define outpw(port,value) *((volatile unsigned int *)(port))=value
#define inpw(port) (*((volatile unsigned int *)(port)))
#define outpb(port,value) *((volatile unsigned char *)(port))=value
#define inpb(port) (*((volatile unsigned char *)(port)))
#define outps(port,value) *((volatile unsigned short *)(port))=value
#define inps(port) (*((volatile unsigned short *)(port)))
#define outp32(port,value) *((volatile unsigned int *)(port))=value
#define inp32(port) (*((volatile unsigned int *)(port)))
#define outp8(port,value) *((volatile unsigned char *)(port))=value
#define inp8(port) (*((volatile unsigned char *)(port)))
#define outp16(port,value) *((volatile unsigned short *)(port))=value
#define inp16(port) (*((volatile unsigned short *)(port)))
#define E_SUCCESS 0
#ifndef NULL
#define NULL 0
#endif
#define TRUE 1
#define FALSE 0
#define ENABLE 1
#define DISABLE 0
/* Define one bit mask */
#define BIT0 0x00000001
#define BIT1 0x00000002
#define BIT2 0x00000004
#define BIT3 0x00000008
#define BIT4 0x00000010
#define BIT5 0x00000020
#define BIT6 0x00000040
#define BIT7 0x00000080
#define BIT8 0x00000100
#define BIT9 0x00000200
#define BIT10 0x00000400
#define BIT11 0x00000800
#define BIT12 0x00001000
#define BIT13 0x00002000
#define BIT14 0x00004000
#define BIT15 0x00008000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
#endif