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Atmel SAM3S1C

The Atmel SAM3S1C is a Core - ARM Cortex-M3 revision 2.0 running at up to 64 MHz - Memory Protection Unit (MPU) - Thumb-2 instruction set Pin-to-pin compatible with AT91SAM7S series (48- and 64-pin versions) Memories - 64 to 256 Kbytes Flash, 128-bit wide access, memory accelerator, single plane - 16 to 48 Kbytes SRAM - 16 Kbytes ROM with embedded bootloader routines (UART, USB) and IAP routines - 8-bit Static Memory Controller (SMC): SRAM, PSRAM, NOR and NAND Flash support System - Embedded voltage regulator for single supply operation - Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog - Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with Failure Detection - High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz default frequency - Slow Clock Internal RC oscillator as permanent low-power mode device clock - Two PLLs up to 130 MHz for device clock and for USB - Temperature Sensor - Up to 22 peripheral DMA (PDC) chns Low Power Modes - Sleep and Backup modes - Ultra low power RTC Peripherals - USB 2.0 Device: 12 Mbps, 2668 byte FIFO, up to 8 bidirectional Endpoints - Up to 2 USARTs with ISO7816, IrDA, RS-485, SPI, Manchester and Modem Mode - Two 2-wire UARTs - Up to 2 Two Wire Interface (I2C compatible), 1 SPI, 1 Serial Synchronous Controller (I2S), 1 High Speed Multimedia Card Interface (SDIO/SD Card/MMC) - Up to 6 Three-chn 16-bit Timer/Counter - 4-chn 16-bit PWM with Complementary Output, Fault Input, 12-bit Dead Time Generator Counter for Motor Control - 32-bit Real-time Timer and RTC with calendar and alarm features - Up to 15-chn, 1Msps ADC - One 2-chn 12-bit 1Msps DAC - One Analog Comparator - 32-bit Cyclic Redundancy Check Calculation Unit (CRCCU) - Write Protected Registers I/O - Up to 79 I/O lines with external interrupt capability - Three 32-bit Parallel Input/Output Controllers.

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Generic User Guide
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Technical Reference Manual
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Header Files
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Device Programmers
MDK Middleware
The following middleware components are pre-configured in MDK-Professional
Real-Time OS
Simulated Features
Simulation for this device is provided by the default peripheral simulation driver.

Complete peripheral simulation is not available and is not planned to be implemented by ARM.

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