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Oregano Systems 8051 IP Core

The Oregano Systems 8051 IP Core is an 8051 compatible IP core, fully synchronous circuit design single clock, 1-4 clock cycles instructions, parametrizeable number of timer and UART units, up to 64 KBytes RAM, up to 64KBytes ROM.

[Chip Vendor]

Development Tools
Compiler, Assembler, Linker, Debugger
Data Sheets
8051 Instruction Set Manual for the Oregano Systems 8051 IP Core
8051 Instruction Set Manual
1,478,015 bytes
Data Sheet for the Oregano Systems 8051 IP Core
Data Sheet
172,348 bytes
User Guide for the Oregano Systems 8051 IP Core
User Guide
151,056 bytes

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Header Files
Example Code
Emulators
Real-Time OS
Simulated Features

The following on-chip peripherals are simulated by the Keil Software µVision Debugger.

AGSI Drivers

The following AGSI Drivers are available for the Keil Software µVision Simulator.

AGDI Drivers

The following AGDI Drivers are available for the Keil Software µVision Debugger.


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