For Oregano Systems 8051 IP Core — Port 3
Simulation support for this peripheral or feature is comprised of:
- Dialog boxes which display and allow you to change peripheral configuration.
- VTREGs (Virtual Target Registers) which support I/O with the peripheral.
These simulation capabilities are described below.
Parallel Port 3 Dialog
This dialog displays the SFR and pins of Port 3.
P3: This is the P3 SFR. The HEX value and value of each
bit is displayed and may be changed from this dialog.
Pins: These are the states of the pins on the simulated
MCU. When used as outputs, these have the same value as the P3 SFR.
When used as inputs (P3.x is 1) you may set the level of the input
pin to high (1) or low (0).
The PORT3 VTREG may be used (from the Command Window or from a
user or signal function) to affect the input values of the simulated
pins of Port 3.
Data Type: unsigned char
The PORTx VTREGs represent the I/O pins of the simulated
MCU for Port 0, Port 1, and so on. PORT0 represents Port 0, PORT1
represents Port 1, etc. You may read PORTx to determine the
state of the output pins of that port. For example, in the command
window, you may type,
to obtain value corresponding to the set pins of Port 0. You may
also change the input values of port pins by changing the value of
the VTREG. For example,
sets the upper four port pins of Port 1 to a value of 1 and the
lower 4 port pins to a value of 0. You may use the bitwise operators
AND(&), OR(|) and XOR(^) to change individual bits of the PORTx
VTREGs. For example:
PORT1 |= 0x01; /* Set P1.0 Pin */
PORT3 &= ~0x02; /* Clr P3.1 Pin */
PORT1 ^= 0x80; /* Toggle P1.7 Pin */