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Nuvoton NUC100RD2AN

The Nuvoton NUC100RD2AN is a + Core - ARM Cortex-M0 core runs up to 50MHz. - NVIC for the 32 interrupt inputs, each with 4-levels of priority. - Serial Wire Debug supports with 2 watchpoints/4 breakpoints. + Widely operating voltage range from 2.5V to 5.5V + Flash EPROM Memory - 32K/64K/128K bytes Flash EPROM for program code. - 4kB flash for ISP loader - Support ISP/IAP program code update + SRAM Memory - 4K/8K/16k bytes embedded SRAM. + PDMA (Peripheral DMA) - Support 9 channels + Clock Control - Build-in 22MHz OSC (Trimmed to 1%) for system operation - Low power 10KHz OSC for watchdog and wakeup sleep operation. - Support one PLL, up to 50MHz, for high performance system operation. - External 12MHz crystal input for precise timing operating. - External 32 kHz crystal input for RTC function and low power system operation. + GPIO - Four I/O modes (bi-direction, Push-Pull, Open-Drain, IN high impendence) + Timers - 4 sets of 24-bit timer with 8-bit pre-scaler. + Watch Dog Timer + RTC + PWM/Capture - up to four 16-bit PWM generators. - Up to eight 16-bit digital Capture timers. - Support Capture interrupt + UART - Up to three compatible 16550 UART devices. - Support IrDA(SIR) and LIN function + SPI - Up to four sets of SPI device. - Master up to 16 Mbps / Slave up to 10 Mbps. + I2C - Two sets of I2C device. - Master/Slave up to 1Mbit/s. + I2S - interface with external audio CODEC. - Operate as either master or slave mode. - Capable of handling 8, 16, and 32 bit word sizes. + ADC - 12-bit 8-ch with 800ksps. - Single scan/single cycle scan/continuous scan + Analog Comparator - 2 comparator analog modules + Temperature sensor - One temperature sensor built-in with 1? resolution. + Brown-out detector - with 4 levels: 4.5V/3.8V/2.7V/2.4V.

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Development Tools
Compiler, Assembler, Linker, Debugger
Evaluation Boards
JTAG Debuggers
Data Sheets
Generic User Guide
953,546 bytes
Reference Manual
6,570,129 bytes
Technical Reference Manual
472,236 bytes

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Header Files
FLASH Utilities
Real-Time OS
Simulated Features
NOTE
Simulation for this device is provided by the default peripheral simulation driver.

Complete peripheral simulation is not available and is not planned to be implemented by ARM.

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