/**************************************************************************//** * @file NUC1xx.h * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for * for the Nuvoton NUC1xx Device Series * @version V1.00 * @date 21. April 2010 * * @note * Copyright (C) 2009 ARM Limited. All rights reserved. * * @par * ARM Limited (ARM) is supplying this software for use with Cortex-M * processor based microcontrollers. This file can be freely distributed * within development tools that are supporting such ARM based processors. * * @par * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * ******************************************************************************/ #ifndef __NUC1xx_H__ #define __NUC1xx_H__ #ifdef __cplusplus extern "C" { #endif /** @addtogroup NUC1xx_Definitions NUC1xx Definitions This file defines all structures and symbols for NUC1xx: - Registers and bitfields - peripheral base address - peripheral ID - PIO definitions @{ */ /******************************************************************************/ /* Processor and Core Peripherals */ /******************************************************************************/ /** @addtogroup NUC1xx_CMSIS NUC1xx CMSIS Definitions Configuration of the Cortex-M0 Processor and Core Peripherals @{ */ /* * ========================================================================== * ---------- Interrupt Number Definition ----------------------------------- * ========================================================================== */ typedef enum IRQn { /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ /****** NUC1xx Specific Interrupt Numbers **********+*********************************************/ BOD_IRQn = 0, /*!< Brownout low voltage detected interrupt */ WDT_IRQn = 1, /*!< Watch Dog Timer interrupt */ EINT0_IRQn = 2, /*!< External signal interrupt from PB.14 pin */ EINT1_IRQn = 3, /*!< External signal interrupt from PB.15 pin */ GPAB_IRQn = 4, /*!< External signal interrupt from PA[15:0] / PB[13:0] */ GPCDE_IRQn = 5, /*!< External interrupt from PC[15:0]/PD[15:0]/PE[15:0] */ PWMA_IRQn = 6, /*!< PWM0 or PWM2 interrupt */ PWMB_IRQn = 7, /*!< PWM1 or PWM3 interrupt */ TMR0_IRQn = 8, /*!< Timer 0 interrupt */ TMR1_IRQn = 9, /*!< Timer 1 interrupt */ TMR2_IRQn = 10, /*!< Timer 2 interrupt */ TMR3_IRQn = 11, /*!< Timer 3 interrupt */ UART0_IRQn = 12, /*!< UART0 interrupt */ UART1_IRQn = 13, /*!< UART1 interrupt */ SPI0_IRQn = 14, /*!< SPI0 interrupt */ SPI1_IRQn = 15, /*!< SPI1 interrupt */ SPI2_IRQn = 16, /*!< SPI2 interrupt */ SPI3_IRQn = 17, /*!< SPI3 interrupt */ I2C0_IRQn = 18, /*!< I2C0 interrupt */ I2C1_IRQn = 19, /*!< I2C1 interrupt */ CAN0_IRQn = 20, /*!< CAN0 interrupt */ CAN1_IRQn = 21, /*!< CAN1 interrupt */ USB_IRQn = 23, /*!< USB FS Device interrupt */ PS2_IRQn = 24, /*!< PS2 interrupt */ ACMP_IRQn = 25, /*!< Analog Comparator-0 or Comaprator-1 interrupt */ PDMA_IRQn = 26, /*!< PDMA interrupt */ PWRWU_IRQn = 28, /*!< Clock ctrl int. for chip wake up from power-down */ ADC_IRQn = 29, /*!< ADC0/1 interrupt */ RTC_IRQn = 31, /*!< Real time clock interrupt */ } IRQn_Type; /* * ========================================================================== * ----------- Processor and Core Peripheral Section ------------------------ * ========================================================================== */ /* Configuration of the Cortex-M0 Processor and Core Peripherals */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ /*@}*/ /* end of group NUC1xx_CMSIS */ #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ #include "system_NUC1xx.h" /* System Header */ /******************************************************************************/ /* Device Specific Peripheral Registers structures */ /******************************************************************************/ #if defined ( __CC_ARM ) #pragma anon_unions #endif /*------------- System Manager Control (GCR) ---------------------------------*/ /** @addtogroup NUC1xx_GCR NUC1xx System Manager Control Block @{ */ typedef struct { uint32_t RESERVED0[1]; __IO uint32_t RSTSRC; /*!< Offset: 0x004 (R/W) System Reset Source Register */ __IO uint32_t IPRSTC1; /*!< Offset: 0x008 (R/W) IP Reset Control Resister 1 */ __IO uint32_t IPRSTC2; /*!< Offset: 0x00C (R/W) IP Reset Control Resister 2 */ uint32_t RESERVED1[2]; __IO uint32_t BODCR; /*!< Offset: 0x018 (R/W) Brown Out Detector Control Register */ uint32_t RESERVED2[5]; __IO uint32_t GPA_MFP; /*!< Offset: 0x030 (R/W) GPIOA multiple function and input type control register */ __IO uint32_t GPB_MFP; /*!< Offset: 0x034 (R/W) GPIOB multiple function and input type control register */ __IO uint32_t GPC_MFP; /*!< Offset: 0x038 (R/W) GPIOC multiple function and input type control register */ __IO uint32_t GPD_MF; /*!< Offset: 0x03C (R/W) GPIOD multiple function and input type control register */ __IO uint32_t GPE_MFP; /*!< Offset: 0x040 (R/W) GPIOE input type control register */ uint32_t RESERVED3[3]; __IO uint32_t USPI_MFP; /*!< Offset: 0x050 (R/W) Multiple function pin for USPI control register */ uint32_t RESERVED4[43]; __IO uint32_t RegLockAddr; /*!< Offset: 0x100 (R/W) Register Lock Key address */ uint32_t RESERVED5[3]; __IO uint32_t RCADJ; /*!< Offset: 0x110 (R/W) RC Adjustment Value */ } NUC_GCR_TypeDef; /*@}*/ /* end of group NUC1xx_GCR */ /*------------- Clock Control (CLK) ------------------------------------------*/ /** @addtogroup NUC1xx_CLK NUC1xx Clock Control Block @{ */ typedef struct { __IO uint32_t PWRCON; /*!< Offset: 0x000 (R/W) System Power Down Control Register */ __IO uint32_t AHBCLK; /*!< Offset: 0x004 (R/W) AHB Devices Clock Enable Control Register */ __IO uint32_t APBCLK; /*!< Offset: 0x008 (R/W) APB Devices Clock Enable Control Register */ uint32_t RESERVED0[1]; __IO uint32_t CLKSEL0; /*!< Offset: 0x010 (R/W) Clock Source Select Control Register 0 */ __IO uint32_t CLKSEL1; /*!< Offset: 0x014 (R/W) Clock Source Select Control Register 1 */ __IO uint32_t CLKDIV; /*!< Offset: 0x018 (R/W) Clock Divider Number Register */ uint32_t RESERVED1[1]; __IO uint32_t PLLCON; /*!< Offset: 0x020 (R/W) PLL Control Register */ } NUC_CLK_TypeDef; /*@}*/ /* end of group NUC1xx_CLK */ /*------------- Interrupt Source Control (INT) ------------------------------------------*/ /** @addtogroup NUC1xx_INT NUC1xx Interrupt Source Control Block @{ */ typedef struct { __I uint32_t IRQ_SRC[32]; /*!< Offset: 0x000 (R/ ) MCU IRQn (IRQn) interrupt source identify */ __IO uint32_t NMI_SEL; /*!< Offset: 0x080 (R/W) NMI source interrupt select control register */ __IO uint32_t MCU_IRQ; /*!< Offset: 0x084 (R/W) MCU IRQ Number identify register */ } NUC_INT_TypeDef; /*@}*/ /* end of group NUC1xx_INT */ /*------------- USB Control (USB) ------------------------------------------*/ /** @addtogroup NUC1xx_USB NUC1xx USB Control Block @{ */ typedef struct { __IO uint32_t BUFSEG; /*!< Offset: +0x00 (R/W) Buffer Segmentation of endpoint */ __IO uint32_t MXPLD; /*!< Offset: +0x04 (R/W) Maximal payload of endpoint */ __IO uint32_t CFG; /*!< Offset: +0x08 (R/W) Configuration of endpoint */ __IO uint32_t CFGP; /*!< Offset: +0x0C (R/W) stall control register and In/out ready clear flag of endpoint */ } NUC_USBD_EP_TypeDef; typedef struct { __IO uint32_t IEF; /*!< Offset: 0x000 (R/W) Interrupt Enable Flag */ __IO uint32_t EFV; /*!< Offset: 0x004 (R/W) Interrupt Event Flag */ __IO uint32_t FADDR; /*!< Offset: 0x008 (R/W) Function Address */ __IO uint32_t STS; /*!< Offset: 0x00C (R/ ) System state */ __IO uint32_t ATTR; /*!< Offset: 0x010 (R/W) Bus state & attribution */ __I uint32_t FLODETB; /*!< Offset: 0x014 (R/ ) Floating detect */ __IO uint32_t BUFSEG; /*!< Offset: 0x018 (R/W) Buffer Segmentation */ uint32_t RESERVED0[1]; NUC_USBD_EP_TypeDef EP[6]; /*!< Offset: 0x020 EndPoint register block */ uint32_t RESERVED1[4]; __IO uint32_t DRVSE0; /*!< Offset: 0x090 (R/W) Force USB PHY to drive SE0 when set to 1 */ uint32_t RESERVED2[3]; __IO uint32_t USBBIST; /*!< Offset: 0x0A0 (R/W) USB buffer test register */ __IO uint32_t PDMA; /*!< Offset: 0x0A4 (R/W) PDMA control register */ } NUC_USBD_TypeDef; /*@}*/ /* end of group NUC1xx_USB */ /*------------- General Purpose Input/Output (GPIO) --------------------------*/ /** @addtogroup NUC1xx_GPIO NUC1xx General Purpose Input/Output @{ */ typedef struct { __IO uint32_t PMD; /*!< Offset: 0x000 (R/W) GPIO Port # Bit Mode Control */ __IO uint32_t SCH; /*!< Offset: 0x004 (R/W) GPIO Port # Bit OFF Digital Enable */ __IO uint32_t DOUT; /*!< Offset: 0x008 (R/W) GPIO Port # Data Output Value */ __IO uint32_t DMASK; /*!< Offset: 0x00C (R/W) GPIO Port # Data Output Write Mask */ __I uint32_t PIN; /*!< Offset: 0x010 (R/ ) GPIO Port # Pin Value */ __IO uint32_t DBEN; /*!< Offset: 0x014 (R/W) GPIO Port # De-bounce Enable */ __IO uint32_t IMD; /*!< Offset: 0x018 (R/W) GPIO Port # Interrupt Mode Control */ __IO uint32_t IEN; /*!< Offset: 0x01C (R/W) GPIO Port # Interrupt Enable */ __IO uint32_t ISRC; /*!< Offset: 0x020 (R/W) GPIO Port # Interrupt Source Flag */ } NUC_GPIO_TypeDef; /*@}*/ /* end of group NUC1xx_GPIO */ /*------------- I2C Serial Interface (I2C) ----------------------------*/ /** @addtogroup NUC1xx_I2C NUC1xx I2C Serial Interface @{ */ typedef struct { __IO uint32_t CON; /*!< Offset: 0x000 (R/W) I2C Control Register */ __IO uint32_t ADRR0; /*!< Offset: 0x004 (R/W) I2C Slave address Register0 */ __IO uint32_t DAT; /*!< Offset: 0x008 (R/W) I2C DATA Register */ __I uint32_t STATUS; /*!< Offset: 0x00C (R/ ) I2C Status Register */ __IO uint32_t CLK; /*!< Offset: 0x010 (R/W) I2C clock divided Register */ __IO uint32_t TOC; /*!< Offset: 0x014 (R/W) I2C Time out control Register */ __IO uint32_t ADDR1; /*!< Offset: 0x018 (R/W) I2C Slave address Register1 */ __IO uint32_t ADDR2; /*!< Offset: 0x01C (R/W) I2C Slave address Register2 */ __IO uint32_t ADDR3; /*!< Offset: 0x020 (R/W) I2C Slave address Register3 */ __IO uint32_t ADM0; /*!< Offset: 0x024 (R/W) Slave address Mask Register0 */ __IO uint32_t ADM1; /*!< Offset: 0x028 (R/W) Slave address Mask Register1 */ __IO uint32_t ADM2; /*!< Offset: 0x02C (R/W) Slave address Mask Register2 */ __IO uint32_t ADM3; /*!< Offset: 0x030 (R/W) Slave address Mask Register3 */ } NUC_I2C_TypeDef; /*@}*/ /* end of group NUC1xx_I2C */ /*------------- PWM Generator and Capture Timer (PWM) ----------------------------*/ /** @addtogroup NUC1xx_PWM NUC1xx PWM Generator and Capture Timer @{ */ typedef struct { __IO uint32_t CNR; /*!< Offset: +0x00 (R/W) PWM Counter Register */ __IO uint32_t CMR; /*!< Offset: +0x04 (R/W) PWM Comparator Register */ __I uint32_t PDR; /*!< Offset: +0x08 (R/ ) PWM Data Register */ } NUC_PWM_CNT_TypeDef; typedef struct { __IO uint32_t CRLR; /*!< Offset: +0x00 (R/W) Capture Rising Latch Register */ __IO uint32_t CFLR; /*!< Offset: +0x04 (R/W) Capture Falling Latch Register */ } NUC_PWM_CHN_TypeDef; typedef struct { __IO uint32_t PPR; /*!< Offset: 0x000 (R/W) PWM Prescaler Register */ __IO uint32_t CSR; /*!< Offset: 0x004 (R/W) PWM Clock Select Register */ __IO uint32_t PCR; /*!< Offset: 0x008 (R/W) PWM Control Register */ NUC_PWM_CNT_TypeDef CNT[4]; /*!< Offset: 0x00C PWM Counter Register Block */ uint32_t RESERVED0[1]; __IO uint32_t PIER; /*!< Offset: 0x040 (R/W) PWM Interrupt Enable Register */ __IO uint32_t PIIR; /*!< Offset: 0x044 (R/C) PWM Interrupt Indication Register */ uint32_t RESERVED1[2]; __IO uint32_t CCR0; /*!< Offset: 0x050 (R/W) Capture Control Register 0 */ __IO uint32_t CCR1; /*!< Offset: 0x054 (R/W) Capture Control Register 1 */ NUC_PWM_CHN_TypeDef CHN[4]; /*!< Offset: 0x058 PWM Channel Register Block */ __IO uint32_t CAPENR; /*!< Offset: 0x078 (R/W) Capture Input Enable Register */ __IO uint32_t POE; /*!< Offset: 0x07C (R/W) PWM Output Enable */ } NUC_PWM_TypeDef; /*@}*/ /* end of group NUC1xx_PWM */ /*------------- Real Time Clock (RTC) ----------------------------*/ /** @addtogroup NUC1xx_RTC NUC1xx Real Time Clock @{ */ typedef struct { __IO uint32_t INIR; /*!< Offset: 0x000 (R/W) RTC Initiation Register */ __IO uint32_t AER; /*!< Offset: 0x004 (R/W) RTC Access Enable Register */ __IO uint32_t FCR; /*!< Offset: 0x008 (R/W) RTC Frequency Compensation Register */ __IO uint32_t TLR; /*!< Offset: 0x00C (R/W) Time Loading Register */ __IO uint32_t CLR; /*!< Offset: 0x010 (R/W) Calendar Loading Register */ __IO uint32_t TSSR; /*!< Offset: 0x014 (R/W) Time Scale Selection Register */ __IO uint32_t DWR; /*!< Offset: 0x018 (R/W) Day of the Week Register */ __IO uint32_t TAR; /*!< Offset: 0x01C (R/W) Time Alarm Register */ __IO uint32_t CAR; /*!< Offset: 0x020 (R/W) Calendar Alarm Register */ __IO uint32_t LIR; /*!< Offset: 0x024 (R/W) Leap year Indicator Register */ __IO uint32_t RIER; /*!< Offset: 0x028 (R/W) RTC Interrupt Enable Register */ __IO uint32_t RIIR; /*!< Offset: 0x02C (R/C) RTC Interrupt Indicator Register */ __IO uint32_t TTR; /*!< Offset: 0x030 (R/W) RTC Time Tick Register */ } NUC_RTC_TypeDef; /*@}*/ /* end of group NUC1xx_RTC */ /*------------- Serial Peripheral Interface (SPI) ----------------------------*/ /** @addtogroup NUC1xx_SPI NUC1xx Serial Peripheral Interface @{ */ typedef struct { __IO uint32_t CNTRL; /*!< Offset: 0x000 (R/W) Control and Status Register */ __IO uint32_t DIVIDER; /*!< Offset: 0x004 (R/W) Clock Divider Register */ __IO uint32_t SSR; /*!< Offset: 0x008 (R/W) Slave Select Register */ uint32_t RESERVED0[1]; __I uint32_t RX[2]; /*!< Offset: 0x010 (R/ ) Data Receive Register */ uint32_t RESERVED1[2]; __O uint32_t TX[2]; /*!< Offset: 0x020 ( /W) Data Transmit Register */ uint32_t RESERVED2[2]; __IO uint32_t JS; /*!< Offset: 0x030 (R/W) Dongle joystick Control Register */ __IO uint32_t VARCLK; /*!< Offset: 0x034 (R/W) Variable Clock Flag Pattern Register */ __IO uint32_t _DMA; /*!< Offset: 0x038 (R/W) SPI DMA control register */ } NUC_SPI_TypeDef; /*@}*/ /* end of group NUC1xx_SPI */ /*------------- Timer (TIM) ----------------------------*/ /** @addtogroup NUC1xx_TIM NUC1xx Timer @{ */ typedef struct { __IO uint32_t CSR; /*!< Offset: 0x000 (R/W) Timer Control and Status Register */ __IO uint32_t CMPR; /*!< Offset: 0x004 (R/W) Timer Compare Register */ __IO uint32_t ISR; /*!< Offset: 0x008 (R/W) Timer Interrupt Status Register */ __I uint32_t DR; /*!< Offset: 0x00C (R/ ) Timer Data Register */ } NUC_TIM_TypeDef; /*@}*/ /* end of group NUC1xx_TIM */ /*------------- Watchdog Timer (WDT) ----------------------------*/ /** @addtogroup NUC1xx_TIM NUC1xx Watchdog Timer @{ */ typedef struct { __IO uint32_t CR; /*!< Offset: 0x000 (R/W) Watchdog Timer Control Register */ } NUC_WDT_TypeDef; /*@}*/ /* end of group NUC1xx_WDT */ /*------------- UART Interface (UART) ----------------------------*/ /** @addtogroup NUC1xx_UART NUC1xx UART Interface @{ */ typedef struct { union { __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */ __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */ }; __IO uint32_t IER; /*!< Offset: 0x004 (R/W) Interrupt Enable Register */ __IO uint32_t FCR; /*!< Offset: 0x008 (R/W) FIFO Control Register */ __IO uint32_t LCR; /*!< Offset: 0x00C (R/W) Line Control Register */ __IO uint32_t MCR; /*!< Offset: 0x010 (R/W) Modem Control Register */ __IO uint32_t MSR; /*!< Offset: 0x014 (R/W) Modem Status Register */ __IO uint32_t FSR; /*!< Offset: 0x018 (R/W) FIFO Status Register */ __IO uint32_t ISR; /*!< Offset: 0x01C (R/W) Interrupt Status Register */ __IO uint32_t TOR; /*!< Offset: 0x020 (R/W) Time Out Register */ __IO uint32_t BAUD; /*!< Offset: 0x024 (R/W) Baud Rate Divisor Register */ __IO uint32_t IRCR; /*!< Offset: 0x028 (R/W) IrDA Control Register */ __IO uint32_t LIN_BCNT; /*!< Offset: 0x02C (R/W) LIN Break Failed Count Register */ __IO uint32_t FUN_SEL; /*!< Offset: 0x030 (R/W) Function Select Register */ } NUC_UART_TypeDef; /*@}*/ /* end of group NUC1xx_UART */ /*------------- Controller Area Network (CAN) ----------------------------*/ /** @addtogroup NUC1xx_CAN NUC1xx Controller Area Network @{ */ typedef struct { __IO uint32_t MODE; /*!< Offset: 0x000 (R/W) Mode Register */ __IO uint32_t CMD; /*!< Offset: 0x004 (R/W) Command Register */ __I uint32_t BSR; /*!< Offset: 0x008 (R/ ) Bus Status Register */ __IO uint32_t INTR; /*!< Offset: 0x00C (R/W) Interrupt Status Register */ __IO uint32_t INTEN; /*!< Offset: 0x010 (R/W) Interrupt Enable Register */ __IO uint32_t BTIM; /*!< Offset: 0x014 (R/W) Bit Timing Register */ uint32_t RESERVED0[2]; __I uint32_t ERRCR; /*!< Offset: 0x020 (R/W) Error Capture Register */ uint32_t RESERVED1[1]; __I uint32_t RECNTR; /*!< Offset: 0x028 (R/W) Receiver Error Counter Register */ __IO uint32_t TECNTR; /*!< Offset: 0x02C (R/W) Transmit Error Counter Register */ __IO uint32_t TXFINFO; /*!< Offset: 0x030 (R/W) Transmit Frame Information Register */ __IO uint32_t TXID; /*!< Offset: 0x034 (R/W) Transmit Identifier Register */ __IO uint32_t TX[2]; /*!< Offset: 0x038 (R/W) Transmit Data Register */ __I uint32_t RXFINFO; /*!< Offset: 0x040 (R/ ) Received Frame Information Register */ __I uint32_t RXID; /*!< Offset: 0x044 (R/ ) Received Identifier Register */ __I uint32_t RX[2]; /*!< Offset: 0x048 (R/ ) Received Data Register */ __IO uint32_t ACR; /*!< Offset: 0x050 (R/W) Acceptance Code Register */ __IO uint32_t AMR; /*!< Offset: 0x05C (R/W) Acceptance Mask Register */ } NUC_CAN_TypeDef; /*@}*/ /* end of group NUC1xx_CAN */ /*------------- PS2 Device Controller (PS2) ----------------------------*/ /** @addtogroup NUC1xx_PS2 NUC1xx PS2 Device Controller @{ */ typedef struct { __IO uint32_t CON; /*!< Offset: 0x000 (R/W) Control Register */ __IO uint32_t TX[2]; /*!< Offset: 0x004 (R/W) Transmit Data Register */ __I uint32_t RX[1]; /*!< Offset: 0x014 (R/ ) Received Data Register */ __IO uint32_t STATUS; /*!< Offset: 0x018 (R/W) Status Register */ __IO uint32_t INTID; /*!< Offset: 0x05C (R/W) Interrupt Identification Register */ } NUC_PS2_TypeDef; /*@}*/ /* end of group NUC1xx_PS2 */ /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ /** @addtogroup NUC1xx_ADC NUC1xx Analog-to-Digital Converter @{ */ typedef struct { __I uint32_t DR[8]; /*!< Offset: 0x000 (R/ ) A/D Data Register */ __IO uint32_t CR; /*!< Offset: 0x020 (R/W) A/D Control Register */ __IO uint32_t CHER; /*!< Offset: 0x024 (R/W) A/D Compare Register */ __IO uint32_t CMPR[2]; /*!< Offset: 0x028 (R/W) A/D Compare Register */ __IO uint32_t SR; /*!< Offset: 0x030 (R/W) A/D Status Register */ __IO uint32_t CALR; /*!< Offset: 0x034 (R/W) A/D Calibration Register */ } NUC_ADC_TypeDef; /*@}*/ /* end of group NUC1xx_ADC */ /*------------- Analog Comparator (ACMP) ----------------------------*/ /** @addtogroup NUC1xx_ACMP NUC1xx Analog Comparator @{ */ typedef struct { __IO uint32_t CMP0CR; /*!< Offset: 0x000 (R/W) CMP0 Control Register */ __IO uint32_t CMP1CR; /*!< Offset: 0x004 (R/W) CMP1 Control Register */ __IO uint32_t CMPSR; /*!< Offset: 0x008 (R/W) CMP Status Register */ } NUC_ACMP_TypeDef; /*@}*/ /* end of group NUC1xx_ACMP */ /*------------- Peripheral Direct Memory Access (PDMA) ----------------------------*/ /** @addtogroup NUC1xx_PDMA NUC1xx Peripheral Direct Memory Access @{ */ typedef struct { __IO uint32_t CSR; /*!< Offset: +0x00 (R/W) PDMA Control Register */ __IO uint32_t SAR; /*!< Offset: +0x04 (R/W) PDMA Source Address Register */ __IO uint32_t DAR; /*!< Offset: +0x08 (R/W) PDMA Destination Address Register */ __IO uint32_t BCR; /*!< Offset: +0x0C (R/W) PDMA Transfer Byte Count Register */ __IO uint32_t POINT; /*!< Offset: +0x10 (R/W) PDMA Internal buffer pointer */ __IO uint32_t CSAR; /*!< Offset: +0x14 (R/W) PDMA Current Source Address Register */ __IO uint32_t CDAR; /*!< Offset: +0x18 (R/W) PDMA Current Destination Address Register */ __IO uint32_t CBCR; /*!< Offset: +0x1C (R/W) PDMA Current Transfer Byte Count Register */ __IO uint32_t IER; /*!< Offset: +0x20 (R/W) PDMA Interrupt Enable Register */ __IO uint32_t ISR; /*!< Offset: +0x24 (R/W) PDMA Interrupt Status Register */ uint32_t RESERVED0[22]; __IO uint32_t SBUF; /*!< Offset: +0x80 (R/W) PDMA Shared Buffer FIFO */ uint32_t RESERVED1[31]; } NUC_PDMA_CHN_TypeDef; typedef struct { NUC_PDMA_CHN_TypeDef CHN[9]; /*!< Offset: 0x000 PDMA Channel block Register */ uint32_t RESERVED0[383]; __IO uint32_t GCRCSR; /*!< Offset: 0xF00 (R/W) PDMA Global Control Register */ __IO uint32_t PDSSR0; /*!< Offset: 0xF04 (R/W) PDMA Service Selection Control Register 0 */ __IO uint32_t PDSSR1; /*!< Offset: 0xF04 (R/W) PDMA Service Selection Control Register 1 */ __IO uint32_t GCRISR; /*!< Offset: 0xF04 (R/W) PDMA Global Interrupt Register */ } NUC_PDMA_TypeDef; /*@}*/ /* end of group NUC1xx_PDMA */ /*------------- Flash Memory Controller (FMC) ----------------------------*/ /** @addtogroup NUC1xx_FMC Flash Memory Controller @{ */ typedef struct { __IO uint32_t ISPCON; /*!< Offset: 0x000 (R/W) ISP Control Register */ __IO uint32_t ISPADR; /*!< Offset: 0x004 (R/W) ISP Address Register */ __IO uint32_t ISPDAT; /*!< Offset: 0x008 (R/W) ISP Data Register */ __IO uint32_t ISPCMD; /*!< Offset: 0x00C (R/W) ISP Command Register */ __IO uint32_t ISPTRG; /*!< Offset: 0x010 (R/W) ISP Trigger Register */ __I uint32_t DFBADR; /*!< Offset: 0x014 (R/ ) Data Flash Start Address */ __IO uint32_t FATCON; /*!< Offset: 0x018 (R/W) Flash Access Window Control Register */ __IO uint32_t ICPCON; /*!< Offset: 0x01C (R/W) ?? */ __IO uint32_t RMPCON; /*!< Offset: 0x020 (R/W) ?? */ } NUC_FMC_TypeDef; /*@}*/ /* end of group NUC1xx_FMC */ #if defined ( __CC_ARM ) #pragma no_anon_unions #endif /******************************************************************************/ /* Peripheral memory map */ /******************************************************************************/ /* Base addresses */ #define NUC_FLASH_BASE (( uint32_t)0x00000000) #define NUC_SRAM_BASE (( uint32_t)0x20000000) #define NUC_AHB_BASE (( uint32_t)0x50000000) #define NUC_APB1_BASE (( uint32_t)0x40000000) #define NUC_APB2_BASE (( uint32_t)0x40100000) /* AHB peripherals */ #define NUC_GCR_BASE (NUC_AHB_BASE + 0x00000) #define NUC_CLK_BASE (NUC_AHB_BASE + 0x00200) #define NUC_INT_BASE (NUC_AHB_BASE + 0x00300) #define NUC_GPIOA_BASE (NUC_AHB_BASE + 0x04000) #define NUC_GPIOB_BASE (NUC_AHB_BASE + 0x04040) #define NUC_GPIOC_BASE (NUC_AHB_BASE + 0x04080) #define NUC_GPIOD_BASE (NUC_AHB_BASE + 0x040C0) #define NUC_GPIOE_BASE (NUC_AHB_BASE + 0x04100) #define NUC_GPIO_DBNCECON_BASE (NUC_AHB_BASE + 0x04180) #define NUC_FMC_BASE (NUC_AHB_BASE + 0x0C000) /* APB1 peripherals */ #define NUC_WDT_BASE (NUC_APB1_BASE + 0x04000) #define NUC_RTC_BASE (NUC_APB1_BASE + 0x08000) #define NUC_TIM0_BASE (NUC_APB1_BASE + 0x10000) #define NUC_TIM1_BASE (NUC_APB1_BASE + 0x10020) #define NUC_I2C0_BASE (NUC_APB1_BASE + 0x20000) #define NUC_SPI0_BASE (NUC_APB1_BASE + 0x30000) #define NUC_SPI2_BASE (NUC_APB1_BASE + 0x34000) #define NUC_PWM_BASE (NUC_APB1_BASE + 0x40000) #define NUC_UART0_BASE (NUC_APB1_BASE + 0x50000) #define NUC_USBD_BASE (NUC_APB1_BASE + 0x60000) #define NUC_ACMP_BASE (NUC_APB1_BASE + 0xD0000) #define NUC_ADC_BASE (NUC_APB1_BASE + 0xE0000) /* APB2 peripherals */ #define NUC_PS2_BASE (NUC_APB2_BASE + 0x00000) #define NUC_TIM2_BASE (NUC_APB2_BASE + 0x10000) #define NUC_TIM3_BASE (NUC_APB2_BASE + 0x10020) #define NUC_I2C1_BASE (NUC_APB2_BASE + 0x20000) #define NUC_SPI1_BASE (NUC_APB2_BASE + 0x30000) #define NUC_SPI3_BASE (NUC_APB2_BASE + 0x34000) #define NUC_UART1_BASE (NUC_APB2_BASE + 0x50000) #define NUC_CAN0_BASE (NUC_APB2_BASE + 0x80000) #define NUC_CAN1_BASE (NUC_APB2_BASE + 0x84000) /******************************************************************************/ /* Peripheral declaration */ /******************************************************************************/ #define NUC_GCR ((NUC_GCR_TypeDef *) NUC_GCR_BASE ) #define NUC_CLK ((NUC_CLK_TypeDef *) NUC_CLK_BASE ) #define NUC_INT ((NUC_INT_TypeDef *) NUC_INT_BASE ) #define NUC_GPIOA ((NUC_GPIO_TypeDef *) NUC_GPIOA_BASE ) #define NUC_GPIOB ((NUC_GPIO_TypeDef *) NUC_GPIOB_BASE ) #define NUC_GPIOC ((NUC_GPIO_TypeDef *) NUC_GPIOC_BASE ) #define NUC_GPIOD ((NUC_GPIO_TypeDef *) NUC_GPIOD_BASE ) #define NUC_GPIOE ((NUC_GPIO_TypeDef *) NUC_GPIOE_BASE ) #define NUC_FMC ((NUC_FMC_TypeDef *) NUC_FMC_BASE ) #define NUC_WDT ((NUC_WDT_TypeDef *) NUC_WDT_BASE ) #define NUC_RTC ((NUC_RTC_TypeDef *) NUC_RTC_BASE ) #define NUC_TIM0 ((NUC_TIM_TypeDef *) NUC_TIM0_BASE ) #define NUC_TIM1 ((NUC_TIM_TypeDef *) NUC_TIM1_BASE ) #define NUC_I2C0 ((NUC_I2C_TypeDef *) NUC_I2C0_BASE ) #define NUC_SPI0 ((NUC_SPI_TypeDef *) NUC_SPI0_BASE ) #define NUC_SPI2 ((NUC_SPI_TypeDef *) NUC_SPI1_BASE ) #define NUC_PWM ((NUC_PWM_TypeDef *) NUC_PWM_BASE ) #define NUC_UART0 ((NUC_UART_TypeDef *) NUC_UART0_BASE ) #define NUC_USBD ((NUC_USBD_TypeDef *) NUC_USBD_BASE ) #define NUC_ACMP ((NUC_ACMP_TypeDef *) NUC_ACMP_BASE ) #define NUC_ADC ((NUC_ADC_TypeDef *) NUC_ADC_BASE ) #define NUC_PS2 ((NUC_PS2_TypeDef *) NUC_PS2_BASE ) #define NUC_TIM2 ((NUC_TIM_TypeDef *) NUC_TIM2_BASE ) #define NUC_TIM3 ((NUC_TIM_TypeDef *) NUC_TIM3_BASE ) #define NUC_I2C1 ((NUC_I2C_TypeDef *) NUC_I2C1_BASE ) #define NUC_SPI1 ((NUC_SPI_TypeDef *) NUC_SPI1_BASE ) #define NUC_SPI3 ((NUC_SPI_TypeDef *) NUC_SPI3_BASE ) #define NUC_UART1 ((NUC_UART_TypeDef *) NUC_UART1_BASE ) #define NUC_CAN0 ((NUC_CAN_TypeDef *) NUC_CAN0_BASE ) #define NUC_CAN1 ((NUC_CAN_TypeDef *) NUC_CAN1_BASE ) #ifdef __cplusplus } #endif #endif /* __NUC1xx_H__ */