RTX51: Interrupt Latency with SiLabs Devices
Information in this article applies to:
Silicon Labs describes an incompatible 8051 behavior on the interrupt system of the F12x and F13x devices that can occur when an instruction that disables an interrupt (like CLR EA) is followed by a single-cycle instruction (like CLR A). Silicon Labs suggests the following remedy (refer to page 154 of Rev 1.4 of the F12x/F13x device datasheet):
RTX51 uses single-cycle instructions after disabling interrupts (both global and individual). Since single-cycle instructions in RTX51 only affect CPU registers, the only side-effect in RTX51 is interrupted latency of high-priority interrupts.
For example, if a low-priority interrupt occurs immediately after interrupts are disabled, the interrupt flag will not be cleared (and interrupts disabled) until the low-priority interrupt begins execution. The effect is that high-priority interrupts are disabled until the low-priority interrupt service routine exits and RTX51 re-enables interrupts.
Subsequently, interrupt response time is increased by the processing time of other low-priority interrupt service routines in your system.
As a solution to this problem, you could rebuild the RTX51 Library with the following changes to the RTXIMASK.INC file:
To rebuild the RTX51 Library:
Note that RTX51Tiny is not affected by the behavior of the Silicon Labs devices.
Last Reviewed: Thursday, February 25, 2021
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