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ARM Cortex-M0+, 15 MHz, 32 kB ROM, 4 kB RAM

The LPC80x are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at CPU frequencies of up to 15 MHz. The LPC804 support up to 32 KB of flash memory and 4 KB of SRAM. The peripheral complement of the LPC80x includes a CRC engine, two I2C-bus interfaces, two USARTs, one SPI interface, Capacitive Touch Interface (Cap Touch), one multi-rate timer, self-wake-up timer, one general purpose 32-bit counter/timer, one 12-bit ADC, one10-bit DAC, one analog comparator, function-configurable I/O ports through a switch matrix, an input pattern match engine, Programmable Logic Unit (PLU), and up to 30 general-purpose I/O pins.

Core ARM Cortex-M0+, 15 MHz
  • Processor:Cortex-M0+, 15 MHz
  • Other:1 x Capacitive Touch Interface
Memory 4 kB RAM, 32 kB ROM
  • ROM:32 kB
  • RAM:4 kB
Communication SPI, I2C, USART
  • SPI:1 x SPI
  • I2C:2 x I2C
Timer/Counter/PWM 4 x 0-bit Timer
  • Watchdog:1 x Windowed Watchdog timer
  • Timer/Counter:4 x 0-bit One 32-bit general purpose, two channel Multi-Rate, Self-Wake-up
Analog 1-channel 10 bit DAC, 1-channel 12 bit ADC, 1 x Comparator
  • ADC:1-channel x 12 bit ADC
  • DAC:1-channel x 10 bit DAC
  • Other:1 x Comparator
I/O & Package 33-QFN
  • I/Os:30 Inputs/Outputs
  • Package, QFN:33-pad HVQFN Package
Development Tools
CMSIS Drivers No CMSIS-Driver in Device Family Pack.
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