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Peripheral Simulation

For NXP (founded by Philips) LPC1765 — Flash Memory IAP

Simulation support for this peripheral or feature is comprised of:

  • Accurate simulation of special on-chip features.

These simulation capabilities are described below.

Flash Memory IAP

The on-chip boot loader code supports 2 Flash memory interfaces:

  • In-System Programming (ISP) programs Flash memory via the UART.
  • In Application Programming (IAP) erases or modifies Flash memory from the user's application code.
Get more information about the
Peripheral Simulation Capabilities
of the µVision Debugger.
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