For Samsung S3F4A2FR — VPB Divider
Simulation support for this peripheral or feature is comprised of:
These simulation capabilities are described below.
VPB Divider Dialog
The VPB Divider Dialog controls the VLSI Peripheral Bus Divider control register. This register controls the VBP clock rate (PCLK) based on the MPU clock rate (CCLK). You may display or change the settings using this dialog.
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Peripheral Simulation Capabilities
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