For NXP (founded by Philips) LPC2102 — APB Divider
Simulation support for this peripheral or feature is comprised of:
These simulation capabilities are described below.
APB Divider Dialog
The APB Divider Dialog controls APBDIV resiter. This register controls the ABP clock rate (PCLK) based on the MPU clock rate (CCLK). You may display or change the settings using this dialog.
Get more information about the
Peripheral Simulation Capabilities
of the µVision Debugger.
of your data.