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Peripheral Simulation

For Silicon Laboratories, Inc. C8051F315 — Power Saving Modes (Idle and Power Down)

Simulation support for this peripheral or feature is comprised of:

  • VTREGs (Virtual Target Registers) which support I/O with the peripheral.

These simulation capabilities are described below.

Data Type: bit

RST simulates the reset pin of the MCU. This pin is bi-directional, allowing an external reset input or a Power On Reset (POR), generated internally, to be output on this pin.

Get more information about the
Peripheral Simulation Capabilities
of the µVision Debugger.
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