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Peripheral Simulation

For STMicroelectronics STR710FZ2 — APB Bridge 1

Simulation support for this peripheral or feature is comprised of:

  • Dialog boxes which display and allow you to change peripheral configuration.

These simulation capabilities are described below.

APB Bridge 1 Dialog

APB Bridge 1

The APB Bridge 1 dialog configures the low-power, APB Bridge of the STR7x device. This bridge interfaces the serial peripherals such as I2C, UART, USB, etc.

Selected Peripheral

  • Peripheral Clock Disable  is checked to disable the peripheral clock for the selected peripheral.
  • Peripheral Reset  is checked to reset the selected peripheral.

Clock Disable & Software Reset

  • APB1_CKDIS (APB Clock Disable Register) contains the peripheral clock disable bit settings.
  • APB1_SWRES (APB Software Reset Register) controls the reset of the APB 1 peripherals.
Get more information about the
Peripheral Simulation Capabilities
of the µVision Debugger.
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