Peripheral Simulation

For Analog Devices ADuC7026 — I²C Interface: I2C1

Simulation support for this peripheral or feature is comprised of:

• Dialog boxes which display and allow you to change peripheral configuration.

These simulation capabilities are described below.

I2C1 Interface - Communication Dialog

The I2C1 Interface - Communication dialog displays the I2C communication activity on the I2C bus. The message Mode, Address, Direction and data message content are displayed for each message. To clear the message display, double-click anywhere in the message display area.

I2C1 Interface - Control Dialog

The I2C1 Interface - Controller dialog configures one of the on-chip I2C controllers. Each I2C controller fully support master or slave operations. The following groups control the simulation of the I2C Interface:

I2C Configuration Group

• I2C1CFG (Configuration Register) controls the basic operating mode of the I2C controller and contains the following control bits:
• Slave Enable is set to enable the slave mode for this controller.
• Master Enable is set to enable the master mode for this controller.
• General Call is set to address every device on the I2C bus.
• HW General Call is set to enable hardware general call.
• Start Back-off Dis. is set to immediately retry a transmission after losing a bus arbitration.
• Loop Back is set to internally connect the transmit and receive signals for test purposes.
• Master Clock is set to generate a serial clock in master mode.

I2C Slave Status Group

• I2C1SSTA (Slave Status Register) contains the following status bits:
• Tx FIFO Empty is set when the slave transmit FIFO is empty.
• Tx FIFO Underflow is set when slave transmit FIFO is underflowing.
• Tx IRQ is set at the end of a transmission.
• Rx IRQ is set after receiving message data.
• Rx FIFO Overflow is set when the receive FIFO overflows.
• No Ack is set when the master requests data and none is available.
• Slave Busy is set when the slave is busy.
• Tx FIFO Flush is set to clear the transmit FIFO.

I2C Master Status Group

• I2C1MSTA (Master Status Register) contains the following status bits:
• Tx FIFO Empty is set when the master transmit FIFO is empty
• Tx IRQ is set at the end of a transmission.
• Rx IRQ is set after receiving message data.
• Rx FIFO Overflow is set when slave receive FIFO overflows.
• No Ack is set when the master receive FIFO is full and the master hasn't acknowledged the received data.
• Arbitration Loss is set when another master has control of the bus.
• Master Busy is set when the master is busy.
• Tx FIFO Flush is set to clear the transmit FIFO

I2C Broadcast Byte

• I2C1BYTE is the byte used for broadcast.

I2C HW Gen. Call ID

• I2C1ALT contains the identifier used when hardware general call is enabled.

I2C Clock Divider Group

• I2C1DIVH contains the high-order byte of the 16-bit divisor term used to calculate the master serial clock.
• I2C1DIVL contains the low-order byte of the 16-bit clock divisor term used to calculate the master serial clock.
• Master Clock contains the calculated master clock frequency.

I2C Slave Data Group

• I2C1SRX contains the last data byte received when in slave mode.
• I2C1STX contains the last data byte sent when in slave mode.

I2C Slave Address ID Group

• I2C1ID0 contains the first byte of the slave device ID.
• I2C1ID1 contains the second byte of the slave device ID.
• I2C1ID2 contains the third byte of the slave device ID.
• I2C1ID3 contains the lastst byte of the slave device ID.

I2C Master Data Group

• I2C1MRX contains the last data byte received when in master mode.
• I2C1MTX contains the last data byte sent when in master mode.

I2C Master Address Group

• I2C1ADR (Master Address Byte Register) contains the address of the slave device. This is transmitted automatically a the start of a tranmit sequence.

I2C Master RX Count Group

• I2C1CNT (Master Data Receive Count Register) contains the number of bytes to be read from the slave device.