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Peripheral Simulation

For NXP (founded by Philips) P89LPC913 — SPI (Serial Peripheral Interface)

Simulation support for this peripheral or feature is comprised of:

  • Dialog boxes which display and allow you to change peripheral configuration.
  • VTREGs (Virtual Target Registers) which support I/O with the peripheral.

These simulation capabilities are described below.

SPI Dialog


The Serial Peripheral Interface Dialog allows you to view and edit the Serial Peripheral Interface (SPI) simulator configuration. Simulation of this interface is controlled by the following groups:

Control Group

  • SPCTL (Serial Peripheral Control Register) contains the following bits that control the functions of the SPI:
  • SSIG (SS Pin Ignore) is set to allow the MSTR bit to determine whether this is a master or a slave. If reset, the state of the SS pin decides this.
  • SPEN (SPI Enable) is set to enable the SPI controller.
  • DORD (Data Order) is set to transmit the least significant bit of the data word first. If reset, the most significant bit is sent first.
  • MSTR (Master Mode) is set to configure this SPI device as a Master.
  • CPOL (Clock Polarity) is set when the SPI clock (SPICLK) is active low. If reset, SPICLK is active high.
  • CPHA (Clock Phase) is set to sample data on the second edge of the SPICLK period.
  • Clock Rate (SPI Clock Rate Select) selects the SPI clock rate divisor when the SPI is configured as a master.
  • SPI Master Clock is the SPI clock value (SPICLK) based on the clock rate setting.

Status Group

  • SPSTAT (SPI Status) contains the following settings:
  • SPIF (SPI Transfer Complete) is set when the SPI completes a data transfer operation. This bit clears after this register and the data register (SPDAT) are read.
  • WCOL (Write Collision Detected) is set when the SPDAT is written while an SPI transfer is still in progress.

Data Group

  • SPDAT (SPI Data Register) contains the either the data to be transmitted or the data received. In Master mode, writing to this register starts data transfer.

Slave Select Group

  • SS# Pin (Slave Select) is the signal level at the slave select pin.

Data Type: unsigned int

The SPI_IN VTREG contains a byte which is received via the MCU SPI (Serial Peripheral Interface) port on the next SPI transfer. You may use this VTREG in a simulation script. For example:

signal void spi_func (void) {
while (1) {
  wwatch (SPI_OUT);
  printf ("SPI_OUT: %2.2X\n", (unsigned) SPI_OUT);
  SPI_IN = SPI_OUT + 1;

This signal function returns the SPI byte send plus 1 on the next SPI transfer.

Data Type: unsigned int

The SPI_OUT VTREG contains a byte output via the MCU SPI (Serial Peripheral Interface) port. When your simulated program sends a byte via SPI, the SPI_OUT VTREG is set with the value output. You may monitor this VTREG in a simulation script. For example:

signal void spi_watcher (void) {
while (1) {
  wwatch (SPI_OUT);
  printf ("SPI_OUT: %2.2X\n", (unsigned) SPI_OUT);
Get more information about the
Peripheral Simulation Capabilities
of the µVision Debugger.
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