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Peripheral Simulation

For NXP (founded by Philips) P89LPC920 — Flash Program Memory with IAP

Simulation support for this peripheral or feature is comprised of:

  • Dialog boxes which display and allow you to change peripheral configuration.

These simulation capabilities are described below.

Flash ROM Dialog

Flash ROM

The Flash Memory dialog displays and allows you to edit the configuration of the on-chip Flash memory capability.

Address Registers Group

  • FMADRH (Program Flash Address High) is the MSB of the Flash page address.
  • FMADRL (Program Flash Address Low) is the LSB of the Flash page address.

Control Register Group

  • FMCON (Flash Memory Control Register) contains the following bit settings:
  • OI (Operation Interrupted) is set when a programming cycle is aborted due to an interrupt or reset.
  • SV (Security Violation) is set when an attempt is made to modify a secured area.
  • HVE (High Voltage Error) is set when the high voltage generator reports an error.
  • HVA (High Voltage Abort) is set if a brownout or an interrupt is detected during a programming cycle or if the brownout detector is disabled at the start of a program or erase cycle.
  • BUSY is set while a programming cycle is in progress.

Data Register Group

  • FMDATA (Flash Data Register) contains the data to be stored in Flash at the page address defined by FMADRH and FMADRL.
Get more information about the
Peripheral Simulation Capabilities
of the µVision Debugger.
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