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Peripheral Simulation

For Atmel AT91M42800A — External Bus Interface

Simulation support for this peripheral or feature is comprised of:

  • Dialog boxes which display and allow you to change peripheral configuration.

These simulation capabilities are described below.

Exernal Bus Interface Dialog

Exernal Bus Interface

The External Bus Interface Dialog controls bus access and chip selects for up to 8 external memory or peripheral devices. The base address, page size, bus width, wait states, and bus access type settings for each chip select are displayed at the top of the dialog. Once selected, a chip select is configured using the following controls:

Selected External Memory

  • EBI_CSRx (Chip Select Register) displays the configuration of the selected chip select. The value is a combination of the other controls in this group.
  • BA (Base Address) contains the most significant bits of the base address. The number of bits in BA changes based on the value of PAGES.
  • DBW (Data Bus Width) is set to 8 or 16-bits.
  • PAGES selects the memory page size of 1, 4, 16 or 64 megabytes.
  • NWS (Number Wait States) sets the number of wait states inserted during an access to the corresponding chip select.
  • TDF (Data Float Output Time) contains the number of wait states for slow memory devices. TDF delays do not affect internal memory accesses.
  • WSE (Wait-State Enable) enables NWS wait states (when checked).
  • BAT (Byte Access Type) enables byte-select access when checked. BAT enables byte-write access when not checked.
  • CSEN enables this chip select when checked.

Memory Control

  • EBI_MCR (Memory Control Register) selects the chip select and memory address lines. Its value is derived from the ALE and DRP settings.
  • ALE (Address Line Enable) controls the combination of valid address lines and valid chip select lines for addressing memory.
  • DRP (Data Read Protocol) enables early read protocol for external memory devices when checked. Standard read protocol is used when not checked.

Abort Status Control

  • EBI_ASR (Abort Status Register) contains information regarding why the Abort happened. Its value is derived from the other controls in this group.
  • ABTTYP (Abort Type Status) contains the type of the processor access (read, write or code fetch).
  • ABTSZ (Abort Size Status) contains the size of the access (byte, word or half-word).
  • UNDADD (Undefined Address Abort Status) is set if an attempt to access an undefined address in the EBI address space occurred.
  • MISADD (Misaligned Address Abort Status) is set if an attempt to access an unaligned address occurred.
  • ARM (Abort Induced by the ARM Core) is set if the ARM core is the source of the abort.
  • PDC (Abort Induced by the Peripheral Data Controller) is set if the Peripheral Data Controller core is the source of the abort.
  • EBI_AASR (Abort Address Status Register) contains the address of the abort.
Get more information about the
Peripheral Simulation Capabilities
of the µVision Debugger.
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