Keil Logo

Peripheral Simulation

For Atmel AT91M55800A — USART0

Simulation support for this peripheral or feature is comprised of:

  • Dialog boxes which display and allow you to change peripheral configuration.

These simulation capabilities are described below.

USART 0 Dialog


The USART 0 Dialog configures USART 0. A USART transfers serial data to and from external devices and the ARM controller. The USART can be configured in a variety of ways to suit the external serial device.

Control Group

  • US0_CR (USART 0 Control Register) displays the combined control information for the following:
  • RXEN (Receiver Enable) click to enable the receiver.
  • TXEN (Transmitter Enable) click to enable the transmitter.
  • RXDIS (Receiver Disable) click to disable the receiver.
  • TXDIS (Transmitter Disable) click to disable the transmitter.
  • RSTRX (Reset Receiver) click to reset the receiver.
  • RSTTX (Reset Transmitter) click to reset the transmitter.
  • RSTSTA (Reset Status Bits) click to reset the Parity Error (PARE), Framing Error (FRAME), Overrun Error (OVRE) and Break Received (RXBRK) status bits.
  • SENDA (Send Address) click to set the address bit with the next character written (multi-drop mode only).
  • STTTO (Start Time-out) click to restart the wait time-out for a new character.
  • STTBRK (Start Break) click to generate a break condition after the next character is sent.
  • STPBRK (Stop Break) click to cancel a break condition.

Mode & Baud Rate Group

  • US0_MR (Mode Register) contains the USART Mode settings which is which is determined by settings of other controls in this group.
  • CHMODE (Channel Mode) selects normal, loopback, echo or remote loopback pin configurations.
  • SYNC (Synchronous Mode Select)
  • CHRL (Character Length) selects the number of bits per character.
  • PAR (Parity Type) selects the generation of even, odd or no parity bits, mark or space, or multi-drop mode.
  • NBSTOP (Number of Stop Bits) selects the number of stop bits to be sent with each character.
  • US0_BRGR (Baud Rate Generator Register) holds the Clock Divisor (CD) value.
  • USCLKS (Clock Selection) selects clock source and type.
  • Baudrate displays the baud rate calculated by the USART.
  • CLKO (Clock Output Select)
  • CD (Clock Divisor) contains the value divided into the clock that determines the baud rate.

Receiver Time-out & Transmitter Time-guard Group

  • US0_RTOR (Receiver Time-out Register) holds the receiver time-out value.
  • TO (Time Out) sets the time-out counter value used with the Start Time-out command.
  • US0_TTGR (Transmitter Time-guard Register) holds the transmitter time guard value.
  • TG (Time-guard) sets the length of time TXD is inactive after each character.

Receiver & Transmitter Group

  • US0_RHR (Receiver Holding Register)
  • RXCHR (Received Character) holds the last character received.
  • US0_THR (Transmitter Holding Register)
  • TXCHR (Character to be Transmitted) holds the next character to be transmitted.

Peripheral Data Controller Group

  • US0_RPR (Receive Pointer Register) holds the receive buffer address.
  • US0_TPR (Transmit Pointer Register) holds the transmit buffer address.
  • US0_RCR (Receive Counter Register) holds the receive counter (RXCTR) value.
  • US0_TCR (Transmit Counter Register) holds the transmit (TXCTR) value.
  • RXCTR (Receive Counter) contains the size of the receive buffer.
  • TXCTR (Transmit Counter) contians the size of the receive buffer.

Interrupt Mask & Channel Status Group

  • US0_IMR (Interrupt Mask Register)
  • US0_CSR (Channel Status Register)
  • TXEMPTY (Transmitter Empty) set if there are no characters in the transmitter hold register(US0_THR).
  • TIMEOUT (Receiver Time-out) set if a Start Time-out counter has elapsed.
  • PARE (Parity Error) set if the controller detects at least 1 false parity bit since the last Reset Status Bits command (RSTSTA).
  • FRAME (Framing Error) set if the controller detects a framing error since the last Reset Status Bits command (RSTSTA).
  • OVRE (Overrun Error) set if the controller detects an overrun condition since the last Reset Status Bits command (RSTSTA).
  • ENDTX (End of Transmitter Transfer) is set if the End of Transmitter signal is active.
  • ENDRX (End of Receiver Transfer) is set if the End of Receiver signal is active.
  • RXBRK (Break Received/End of Break) is set if the USART receives a break since the last Reset Status Bits command (RSTSTA).
  • TXRDY (Transmitter Ready) set if the transmit hold register (US0_THR) is empty and there is no break request pending.
  • RXRDY (Receiver Ready) set when the USART receives at least 1 character and the receiver hold register (US0_RHR) is not empty.
Get more information about the
Peripheral Simulation Capabilities
of the µVision Debugger.
  Arm logo
Important information

This site uses cookies to store information on your computer. By continuing to use our site, you consent to our cookies.

Change Settings

Privacy Policy Update

Arm’s Privacy Policy has been updated. By continuing to use our site, you consent to Arm’s Privacy Policy. Please review our Privacy Policy to learn more about our collection, use and transfers
of your data.