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Peripheral Simulation

For Infineon C515C-L — SSC Interface

Simulation support for this peripheral or feature is comprised of:

  • Dialog boxes which display and allow you to change peripheral configuration.
  • VTREGs (Virtual Target Registers) which support I/O with the peripheral.

These simulation capabilities are described below.

SSC Interface Dialog

SSC Interface

The SSC Interface Dialog controls the Synchronous Serial Channel (SSC) unit of the C515C microcontroller. It supports half or full duplex operation. The application software can use this interface to interconnect with other microcontrollers in a master/slave architecture.


  • SSCCON (SSC Control Register) contains the control flags that setup the SSC mode and baud rate.
  • SCEN (SSC System Enable) is set enable the SSC unit.
  • TEN (Slave Mode - Transmitter Enable) is set to allow the transmitter output to drive the STO output signal in Slave mode.
  • MSTR (Master Mode Selection) is set to configure this unit as the master unit. If reset, it is configured as a slave unit.
  • CPOL (Clock Polarity) is set to configure the shift clock's idle state to high. If reset, the clock's idle state is low.
  • CPHA (Clock Phase) is set to shift data out on the 1st clock edge, then sample data in on the second edge. It is reset to sample data in on the 1st edge, and shift data out on the second edge.
  • Baud Rate selects the oscillator frequency divisor used to generate the baud rate.
  • SSC Master Clock is the master clock output or slave clock input, depending on the setting of MSTR.


  • SCF (SSC Status Register) contains the Write Collision Detect and Transfer Complete status values.
  • TC (Transfer Complete) is set when the last transfer of data completes. This bit is automatically reset when the SSC Status Register (SCF) is read.
  • WCOL (Write Collision Detect) is set an attempt is made to write to the transmit buffer (STB) before the previous data transfer completed. This bit is automatically reset when the SSC Status Register (SCF) is read.


  • SSCMOD (SSC Test Mode) contains the test mode controls. These modes are designed for factory testing and aren't used in normal operation.
  • LOOPB (Loopback Enable) is set to internally connect STO output to the SRI input through an inverter.
  • TRIO (Disable Tri-state Mode of SSC Inputs) is set to test the SSC in Slave mode by connecting the SSC inputs to the output latch of the corresponding port pin.
  • LSBSM (LSB Shift Mode) is set to shift data out of the SSC LSB first. It is reset to shift the data's MSB first.

Slave Select

  • SLS# (Slave Select Pin) is an active-low signal that controls data being shifted into or out of the SSC when is Slave mode.


  • STB (SSC Transmit Buffer Register) contains the data to be transmitted.
  • SRB (SSC Receive Buffer Register) contains the data received from the last transfer.

Data Type: unsigned int

The SSCIN VTREG contains the SSC (Synchronous Serial Interface) input data received by the simulated MCU. Values you write to SSCIN are received immediately (in slave mode) or when the next byte is transmitted (in master mode). The following command causes the MCU to receive the byte 0x12:

SSCIN = 0x12

In slave mode, the SSCCLK VTREG must be set to the external slave mode input clock frequency. For example, the following debugger function may be used receive Synchronous Serial Interface data:

func void SSC_MCUIn (char b) {
  SSCCLK = 1000;   /* SSC Clock in Hz */
  SSCIN = b;

Data Type: unsigned long

The SSCCLK VTREG specifies the Synchronous Serial Interface frequency in hertz when operating in slave mode. For example:

SSCCLK = 100

sets the time for a 1-byte transfer to 0.01 seconds.

Data Type: unsigned int

The SSCOUT VTREG contains the SSC (Synchronous Serial Interface) output data transmitted from the simulated MCU. The following debugger signal function outputs the HEX value of bytes transmitted using the Synchronous Serial Interface.

signal void SSC_MCUOut (void) {
  while (1) {
    printf ("SSC Output %2.2X\n", (unsigned) SSCOUT);
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Peripheral Simulation Capabilities
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