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CAST, Inc. L8051XC1-515

The CAST, Inc. L8051XC1-515 is a Flexible configurable, 12-clock-cycle 8051 compatible IP core timing-compatible to the legacy 80C51 and selected peripherals from the 80C515/517. *** This core is configured with the Dual 80517-like DPTR *** Optional features: 32 I/O lines, three 16-bit timer/counters, compare/capture unit (CCU), 18 interrupts/4 priority levels or 6 interrupts/2 priority levels, two serial interfaces (UARTs), 16-bit multiplication-division unit (MDU), 15-bit programmable watchdog timer, power management unit (PMU). Optionally available: On-Chip Debug Support with JTAG or SWAT (Single Wire Asynchronous Interface) for Keil uVision Debugger. The L8051XC1 IP core can be implemented in FPGA and ASIC.


Data Sheets
Data Sheet
135,699 bytes

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Header Files
Simulated Features
Simulation for this device is provided by the default peripheral simulation driver.

Complete peripheral simulation is not available and is not planned to be implemented by ARM.

The following on-chip peripherals are simulated by the Keil Software µVision Debugger.

AGDI Drivers

The following AGDI Drivers are available for the Keil Software µVision Debugger.

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