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Silicon Laboratories, Inc. EFM32WG395F128

The Silicon Laboratories, Inc. EFM32WG395F128 is an ARM Cortex-M4 CPU platform High Performance 32-bit processor @ up to 48 MHz DSP instruction support and floating-point unit Memory Protection Unit Flexible Energy Management System 256/128/64 KB Flash 32/32/32 KB RAM 93 General Purpose I/O pins Configurable peripheral I/O locations 16 asynchronous external interrupts 12 Channel DMA Controller 12 Channel Peripheral Reflex System (PRS) for autonomous inter-peripheral signaling Hardware AES with 128/256-bit keys in 54/75 cycles 4x 16-bit Timer/Counter 4x3 Compare/Capture/PWM channels 16-bit Low Energy Timer 1x 24-bit Real-Time Counter and 1x 32-bit Real-Time Counter 3x 16/8-bit Pulse Counter Watchdog Timer with dedicated RC oscillator @ 50nA Backup Power Domain external Bus Interface for up to 4x 4x256 MB of external memory mapped space TFT Controller with Direct Drive 3x Universal Synchronous/Asynchronous Receiver/Transmitter uART/SPI/SmartCard (ISO 7816) /IrDA /I2S 2x Universal Asynchronous Receiver/Transmitter 2x Low EnergyuART Autonomous operation with DMA in Deep Sleep Mode 2x I2C Interface with SMBus support Address recognition in Stop Mode Universal Serial Bus (USB) with Host & OTG support Fully USB 2.0 compliant On-chip PHY and embedded 5V to 3.3V regulator Ultra low power precision analog peripherals 12-bit 1 Msamples/s analog to Digital Converter 8 single ended channels/4 differential channels On-chip temperature sensor 12-bit 500 ksamples/s Digital to analog Converter 2x analog Comparator Capacitive sensing with up to 16 inputs 3x Operational Amplifier 6.1 MHz GBW, Rail-to-rail, Programmable Gain Supply Voltage Comparator Low Energy Sensor Interface (LESENSE) Autonomous sensor monitoring in Deep Sleep Mode Pre-Programmed Serial BL.

[Chip Vendor] [Distributors]

Development Tools
Compiler, Assembler, Linker, Debugger
JTAG Debuggers
FLASH Utilities
Real-Time OS
Simulated Features
Simulation for this device is provided by the default peripheral simulation driver.

Complete peripheral simulation is not available and is not planned to be implemented by ARM.

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