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Cadence Design Systems Inc. R8051XC2-BF

The Cadence Design Systems Inc. R8051XC2-BF is a fixed configuration, single-clock 8051 compatible IP core with 11.1 times more performance than the legacy 80C51 (with Dhrystone v1.1 Benchmark on identical clock speed). Optional features: 32 I/O lines, three 16-bit timer/counters, compare/capture unit (CCU), 13 interrupts/4 priority levels, two serial interfaces (UARTs), 16-bit multiplication-division unit (MDU), dual DPTR, 15-bit programmable watchdog timer, power management unit (PMU), internally and externally generated wait states, program and data memory address spaces of 64kB each. Optionally available: On-Chip Debug Support for Keil uVision Debugger. The R8051XC IP core can be implemented in FPGA and ASIC.

[Chip Vendor] [Distributors]

Development Tools
Compiler, Assembler, Linker, Debugger
Data Sheets
R8051XC2 Data Sheet
121,382 bytes

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Header Files
Real-Time OS
Simulated Features

The following on-chip peripherals are simulated by the Keil Software µVision Debugger.

AGSI Drivers

The following AGSI Drivers are available for the Keil Software µVision Simulator.

AGDI Drivers

The following AGDI Drivers are available for the Keil Software µVision Debugger.

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