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The Atmel SAM4CMP8C CM4P0 is an Application/ Master Core - ARM Cortex-M4 running at up to 120 MHz - Memory Protection Unit (MPU) - Memories - Up to 1 Mbyte of Embedded Flash - 128 Kbytes of Embedded SRAM (SRAM0) - 8 Kbytes ROM with embedded boot loader (UART), In-Application Programming (IAP) routines Coprocessor - ARM Cortex-M4F running at up to 120 MHz - Single precision Floating-Point Unit (FPU) - Memories - 16 Kbytes of Embedded SRAM (SRAM1) - 8 Kbytes of Embedded SRAM (SRAM2) Symmetrical/Asynchronous Dual Core Architecture - Interrupt-based Interprocessor Communication Cryptography Safety - 4 Physical Anti-tamper Detection I/O - Security bit for Device Protection Shared System Controller - Power Supply - Embedded Core and LCD Voltage Regulator - Power-on-Reset (POR), Brownout Detector (BOD), Dual Watchdog - Ultra-low-power Backup mode - Clock - Optional 3 to 20 MHz Quartz or ceramic resonator osc. - Ultra-low-power 32.768 kHz crystal osc. - High precision 4/8/12 MHz internal RC osc. - High Frequency PLL up to 240 MHz, 8 MHz PLL with internal 32 kHz input - Low power Slow Clock Internal RC osc. - Ultra low-power RTC - Up to 23 peripheral DMA (PDC) channels Shared Peripherals - Segmented LCD Controller - Up to 5 USARTs (ISO7816, IrDA, RS-485, SPI, Manchester Mode) - 2 2-wire UARTs with one UART (UART1) - 2 400 kHz Master/Slave and Multi-Master Two-wire Interface (I2C compatible) - Up to 7 Serial Peripheral Interface (SPI) - 2 3-Channel 16-bit Timer/Counter - 4-channel 16-bit Pulse Width Modulator - 32-bit Real-time Timer Energy Metering Analog-Front-End - Two-phase (SAM4CMS) or three-phase (SAM4CMP) Energy Metering Analog-Front-End Analog Conversion Block - 8-channel, 10-Bit SAR ADC - SW Controlled On-Chip Reference ranging from 1.6V to 3.4V - Temperature Sensor and Backup Battery Voltage Measurement Channel I/O - 57 I/O lines with external interrupt capability.

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Technical Reference Manual
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Header Files
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Real-Time OS
Simulated Features
Simulation for this device is provided by the default peripheral simulation driver.

Complete peripheral simulation is not available and is not planned to be implemented by ARM.

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