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Atmel SAMG53G19

The Atmel SAMG53G19 is a Core - ARM Cortex-M4 up to 48 MHz - Memory Protection Unit (MPU) - DSP Instruction - Floating Point Unit (FPU) Memories - 512 Kbytes Single Bank embedded Flash - 96 Kbytes embedded SRAM System - Embedded voltage regulator for single-supply operation - Power-on reset (POR) and Watchdog for safe operation - Quartz or ceramic resonator oscillators: 3 to 20 MHz with clock failure detection and 32.768 kHz for RTT or device clock - High-precision 8/16/24 MHz factory-trimmed internal RC oscillator - Slow clock internal RC oscillator as permanent low-power mode device clock - PLL range from 24 MHz to 48 MHz for device clock - 28 peripheral DMA (PDC) channels - 8 x 32-bit General-Purpose Backup Registers (GPBR) - 16 external interrupt lines Power consumption in active mode - 102 uA/MHz running Fibonacci in SRAM Low power modes (typical value) - Wait mode down to 8 uA - Wake-up time less than 5 us - Asynchronous partial wake-up (SleepWalkingâ„¢) Peripherals - 1 USART with SPI mode - 2 Inter-IC Sound Controllers (I2S) - Two-way one-channel Pulse Density Modulation (PDM) - 2 two-wire UARTs - 3 Two-wire Interface (TWI) modules (2 TWI masters, 1 high-speed TWI slave) - 1 fast SPI at up to 24Mbit/s - 2 three-channel 16-bit Timer/Counters (TC) with capture, waveform, compare and PWM modes - 1 32-bit Real-Time Timer (RTT) I/O - Up to 38 I/O lines with external interrupt capability - 2 up to 25-bit PIO Controllers Analog - 1 8-channel 12-bit ADC, up to 800 KSps.

[Chip Vendor] [Distributors]

Development Tools
Compiler, Assembler, Linker, Debugger
JTAG Debuggers
Data Sheets
4,022,214 bytes
Generic User Guide
1,755,988 bytes
Technical Reference Manual
935,507 bytes

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Header Files
FLASH Utilities
Real-Time OS
Simulated Features
Simulation for this device is provided by the default peripheral simulation driver.

Complete peripheral simulation is not available and is not planned to be implemented by ARM.

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