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Spansion MB9BF328S

The Spansion MB9BF328S is a 32-bit ARM Cortex-M3 Core (r2p1) - Up to 60 MHz Frequency Operation - Integrated Nested Vectored Interrupt Controller (NVIC) - 24-bit System timer (Sys Tick) On-chip Memories - Up to 1.5 Mbytes Main Flash - 64 Kbytes Work Flash - SRAM0: Up to 96 Kbytes (connected to I-code bus or D-code bus) - SRAM1: Up to 96 Kbytes (connected to System bus) Multi-function Serial Interface (Max 16chn) - UART, CSIO, LIN, I2C DMA Controller (8chn) External Bus Interface A/D Converter (Max 24chn) - 12-bit A/D Converter D/A Converter (Max 2chn) - 10-bit resolution Base Timer (Max 16chn) -Operation mode: 16-bit PWM, 16-bit PPG, 16/32-bit reload, 6/32-bit PWC General-Purpose I/O Port - Up to 154 high-speed general-purpose I/O Dual Timer (32/16-bit Down Counter) Quadrature Position/Revolution Counter (QPRC) (Max 2chn) Multi-function Timer - 16-bit free-run timer x 3ch. - Input capture x 4ch. - Output compare x 6ch. - A/D activating compare x 3ch. - Waveform generator x 3ch. - 16-bit PPG timer x 3ch. Real-time clock (RTC) HDMI-CEC/Remote control (Max 2chn) Watch Counter USB2.0(Function/Host) External Interrupt Controller Unit - Up to 32 external interrupt input pins - Include one non-maskable interrupt (NMI) input pin Watchdog Timer (2chn) CRC (Cyclic Redundancy Check) Accelerator Built-in CR Clock and Reset - 5 clock sources (2 ext. osc, 2 CR osc, and PLL) - 6 Reset sources (INITX pin, POR, SW, Watchdog, LVD, CSV) Clock Super Visor (CSV) Low-Voltage Detector (LVD) - LVD1: error reporting via interrupt - LVD2: auto-reset operation Low-Power Consumption Mode - 6 low-power consumption modes SLEEP, TIMER, RTC, STOP, Deep standby RTC, Deep standby STOP Debug - Serial Wire JTAG Debug Port (SWJ-DP) - Embedded Trace Macrocells (ETM) Unique ID.

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Development Tools
Compiler, Assembler, Linker, Debugger
JTAG Debuggers
Data Sheets
Data Sheet
4,095,800 bytes
Generic User Guide
1,364,135 bytes
Technical Reference Manual
1,106,603 bytes

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Header Files
FLASH Utilities
Real-Time OS
Simulated Features
Simulation for this device is provided by the default peripheral simulation driver.

Complete peripheral simulation is not available and is not planned to be implemented by ARM.

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