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Spansion MB9AFA42M

The Spansion MB9AFA42M is a 32-bit ARM Cortex-M3 Core (r2p1) - Up to 40 MHz Frequency Operation - Integrated Nested Vectored Interrupt Controller (NVIC) - 24-bit System timer (Sys Tick) On-chip Memories - Up to 256 Kbytes Main Flash - 32 Kbytes Work Flash - SRAM0: Up to 16 Kbytes (connected to I-code bus or D-code bus) - SRAM1: Up to 16 Kbytes (connected to System bus) External Bus Interface (not MB9AFB41LA/FB42LA/FB44LA) - Supports SRAM, NOR Flash memory device - Up to 8 chip selects - 8/16-bit Data width - Up to 25-bit Address bit LCD Controller (LCDC) Multi-function Serial Interface (Max 8chn) - UART, CSIO, I2C DMA Controller (8chn) A/D Converter (Max 24chn) - 12-bit A/D Converter Base Timer (Max 8chn) -Operation mode: 16-bit PWM, 16-bit PPG, 16/32-bit reload, 6/32-bit PWC General-Purpose I/O Port - Up to 83 high-speed general-purpose I/O Dual Timer (32/16-bit Down Counter) HDMI-CEC / Remote Control Receiver (Max 2chn) Real-time clock (RTC) Watch Counter External Interrupt Controller Unit - Up to 16 external interrupt input pins - Include non-maskable interrupt (NMI) input pin Watchdog Timer (2chn) CRC (Cyclic Redundancy Check) Accelerator Clock and Reset - 5 clock sources (2 ext. osc, 2 CR osc, and PLL) - 6 Reset sources (INITX pin, POR, SW, Watchdog, LVD, CSV) Clock Super Visor (CSV) Low-Voltage Detector (LVD) - LVD1: error reporting via interrupt - LVD2: auto-reset operation Low-Power Consumption Mode - 6 low-power consumption modes SLEEP, TIMER, RTC, STOP, Deep standby RTC, Deep standby STOP Debug - Serial Wire JTAG Debug Port (SWJ-DP) - Embedded Trace Macrocells (ETM): MB9AFA41LA/MA, FA42LA/MA and FA44LA/MA support only SWJ-DP Unique ID (41-bit).

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Development Tools
Compiler, Assembler, Linker, Debugger
JTAG Debuggers
Data Sheets
Data Sheet
1,515,934 bytes
Generic User Guide
1,364,135 bytes
Technical Reference Manual
1,106,603 bytes

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Header Files
FLASH Utilities
Real-Time OS
Simulated Features
Simulation for this device is provided by the default peripheral simulation driver.

Complete peripheral simulation is not available and is not planned to be implemented by ARM.

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