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Nuvoton NUC200SD2AN

The Nuvoton NUC200SD2AN is a Core - ARM Cortex-M0 core running up to 50 MHz - Supports low power sleep mode - NVIC for the 32 interrupt inputs, with 4-levels of priority - Serial Wire Debug Flash Memory - 32K/64K/128K bytes Flash for program code - 4 KB flash for ISP loader - ISP/IAP application code update - Configurable data flash address and size for 128 KB system - fixed 4 KB data flash for the 32 KB, 64 KB system SRAM Memory - 8K/16K bytes embedded SRAM PDMA (Peripheral DMA) - 9 channels Clock Control - Built-in 22.1184 MHz high speed oscillator for system operation - Built-in 10 kHz low speed oscillator for Watchdog Timer and Wake-up operation - PLL, up to 50 MHz, for high performance system operation - External 4~24 MHz high speed crystal input - External 32.768 kHz low speed crystal input GPIO - 4 I/O modes (Quasi-bidirectional, Push-pull output, Open-drain output, Input only with high impendence) Timer - 4 sets of 32-bit timers Watchdog Timer Window Watchdog Timer RTC - RTC counter (second, minute, hour), calendar counter (day, month, year) PWM/Capture - Up to 4 built-in 16-bit PWM generators UART - Up to 3 UART controllers - IrDA (SIR), LIN, RS-485 9 bit mode SPI - Up to 4 sets of SPI controllers I2C - Up to 2 sets of I2C device I2S - Interface with external audio CODEC - Capable of handling 8-, 16-, 24- and 32-bit word sizes PS/2 Device - Host communication inhibit and request to send detection USB 2.0 Full-Speed Device - On-chip USB Transceiver ADC - 12-bit SAR ADC with 760 kSPS Analog Comparator - Up to 2 analog comparators Smart Card Host (SC) - up to 3 ISO-7816-3 ports 96-bit unique ID (UID) One built-in temperature sensor Brown-out Detector - With 4 levels: 4.4 V/3.7 V/2.7 V/2.2 V.

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Development Tools
Compiler, Assembler, Linker, Debugger
JTAG Debuggers
Data Sheets
Generic User Guide
953,546 bytes
Reference Manual
8,671,615 bytes
Technical Reference Manual
472,236 bytes

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Header Files
FLASH Utilities
Real-Time OS
Simulated Features
Simulation for this device is provided by the default peripheral simulation driver.

Complete peripheral simulation is not available and is not planned to be implemented by ARM.

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