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Texas Instruments TM4C129CNCPDT

The Texas Instruments TM4C129CNCPDT is an ARM Cortex-M4F Processor Core - 120-MHz operation; 150 DMIPS performance - ARM Cortex SysTick Timer - Nested Vectored Interrupt Controller (NVIC) - IEEE754-compliant single-precision floating-point unit - Memory Protection Unit (MPU) On-Chip Memory - 1024 KB Flash - 256 KB SRAM - 6 KB EEPROM - Internal ROM loaded with TivaWare for C Series software External Peripheral Interface (EPI) - 8-/16-/32- bit dedicated interface for peripherals and memory Cyclical Redundancy Check (CRC) Hardware - 16-/32-bit Hash function that supports 4 CRC forms Advanced Encryption Standard (AES) - HW accelerated data en/decryption based on 128-­,192-­, and 256-­bit keys Data Encryption Standard (DES) - Block cipher implementation with 168-­bit effective key length HW Accelerated Hash (SHA/MD5) - Advanced hash engine that supports SHA-­1, SHA-­2 or MD5 Hash computation Tamper - Support for 4 tamper inputs and configurable tamper event response Communication Interfaces - 8 UARTs - 4 SSI modules with Bi-, Quad- and advanced SSI support - 10 I2C modules with 4 transmission speeds including high-speed mode - 2 CAN 2.0 A/B controllers - USB 2.0 OTG/Host/Device with ULPI interface option and Link Power Management (LPM) support System Integration - ARM PrimeCell 32-chn configurable uDMA controller - 8 16/32-bit GPTM blocks - 2 watchdog timers - Low-power battery-backed Hibernation module - 15 physical GPIO blocks Advanced Motion Control - 1 PWM module with 4 PWM generator blocks and a control block, for a total of 8 PWM outputs - 1 QEI module Analog Support - 2 12-bit ADC modules with a maximum sample rate of 2 million samples/sec - 3 independent integrated analog comparators - 16 digital comparators JTAG and ARM Serial Wire Debug (SWD) 128-pin TQFP package.

[Chip Vendor] [Distributors]

Development Tools
Compiler, Assembler, Linker, Debugger
JTAG Debuggers
Data Sheets
Generic User Guide
1,755,988 bytes
Technical Reference Manual
935,507 bytes

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Header Files
FLASH Utilities
Real-Time OS
Simulated Features
Simulation for this device is provided by the default peripheral simulation driver.

Complete peripheral simulation is not available and is not planned to be implemented by ARM.

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