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Microsemi M2S005

The Microsemi M2S005 is a Microcontroller Subsystem (MSS) - Hard 166 MHz 32-Bit ARM Cortex-M3 Processor (r2p1) Embedded Trace Macrocell (ETM) Memory Protection Unit (MPU) JTAG Debug (4 wires), SW Debug (SWD, 2wires), SW Viewer (SWV) - 64 KB Embedded SRAM (eSRAM) - Up to 512 KB Embedded Nonvolatile Memory (eNVM) - Triple Speed Ethernet (TSE) 10/100/1000 Mbps MAC - USB 2.0 High Speed On-The-Go (OTG) Controller with ULPI Interface - CAN Controller, 2.0B Compliant, Conforms to ISO11898-1 - 2 Each: SPI, I2C, Multi-Mode UARTs (MMUART) Peripherals - Hardware Based Watchdog Timer - 1 General Purpose 64-Bit (or two 32-bit) Timer(s) - Real-Time Calendar/Counter (RTC) - DDR Bridge (4 Port Data R/W Buffering Bridge to DDR Memory) with 64-Bit AXI IF - 2 AHB/APB Interfaces to FPGA Fabric (master/slave capable) - 2 DMA Controllers to Offload Data Transactions from the Cortex-M3 Processor - 8-Channel Peripheral DMA (PDMA) - High Performance DMA (HPDMA) Clocking Resources - Clock Sources Up to 2 High Precision 32 KHz to 20 MHz Main Crystal Oscillator 1 MHz Embedded RC Oscillator 50 MHz Embedded RC Oscillator - Up to 8 Clock Conditioning Circuits (CCCs) Output Clock with 8 Output Phases Frequency: Input 1 to 200 MHz, Output 20 to 400MHz High Speed Serial Interfaces - Up to 16 SERDES Lanes, Each Supporting: XGXS/XAUI Extension (to implement a 10 Gbps (XGMII) Ethernet PHY interface) Native SERDES Interface Facilitates Implementation of Serial RapidIO PCI Express (PCIe) Endpoint Controller High Speed Memory Interfaces - Up to 2 High Speed DDRx Memory Controllers MSS DDR (MDDR) and Fabric DDR (FDDR) Controllers Supports LPDDR/DDR2/DDR3 Maximum 333 MHz Clock Rate SECDED Enable/Disable Feature Supports Various DRAM Bus Width Modes, x16, x18, x32, x36 - SDRAM Support.

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Development Tools
Compiler, Assembler, Linker, Debugger
JTAG Debuggers
Data Sheets
7,571,478 bytes
Generic User Guide
1,364,135 bytes
Technical Reference Manual
1,106,603 bytes

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FLASH Utilities
Real-Time OS
Simulated Features
Simulation for this device is provided by the default peripheral simulation driver.

Complete peripheral simulation is not available and is not planned to be implemented by ARM.

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