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Infineon XMC1302-200

The Infineon XMC1302-200 is a CPU Core - High Performance 32-bit Cortex-M0 CPU - Single cycle 32-bit hardware multiplier - System timer (SysTick) for Operating System support - Ultra low power consumption - Nested Vectored Interrupt Controller (NVIC) - Event Request Unit (ERU) for programmable processing of ext./int. service requests - MATH Co-processor (MATH), consists of a CORDIC unit and a division unit On-Chip Memories - 8 kbytes boot ROM - 16 kbytes high-speed SRAM - up to 200 kbytes Flash program and data memory Communication Peripherals - 2 Universal Serial Interface Channels (USIC), usable as UART, double-SPI, quad-SPI, IIC, IIS,LIN interfaces Analog Frontend Peripherals - A/D Converters (VADC and SHS), 12 channels - Up to 8 channels of out of range comparators (ORC) - Up to 3 fast analog comparators (ACMP) Industrial Control Peripherals - Capture/Compare Units 4 (CCU4) - Capture/Compare Units 8 (CCU8) - Position Interfaces (POSIF) - Brightness and Colour Control Unit (BCCU) System Control - Window Watchdog Timer (WDT) - Temperature Sensor (TSE) - Real Time Clock module with alarm support (RTC) - System Control Unit (SCU) - Pseudo random number generator (PRNG) Input/Output Lines - Tri-stated in input mode - Push/pull or open drain output mode - Configurable pad hysteresis On-Chip Debug Support - standard ARM serial wire debug (2-pin) or the single pin debug (SPD) interface - A breakpoint unit (BPU) supporting up to 4 hardware breakpoints - A watchpoint unit (DWT) supporting up to 2 watchpoints.

[Chip Vendor] [Distributors]

Development Tools
Compiler, Assembler, Linker, Debugger
JTAG Debuggers
Data Sheets
Generic User Guide
953,546 bytes
Technical Reference Manual
472,236 bytes

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Header Files
FLASH Utilities
Real-Time OS
Simulated Features
Simulation for this device is provided by the default peripheral simulation driver.

Complete peripheral simulation is not available and is not planned to be implemented by ARM.

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