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Infineon XMC4100-128

The Infineon XMC4100-128 is a CPU Core - High Performance 32-bit ARM Cortex-M4 CPU with FPU - 80 MHz maximum frequency - DSP/MAC instructions - System timer (SysTick) for Operating System support - Floating Point Unit (FPU) - Memory Protection Unit (MPU) - Nested Vectored Interrupt Controller - General Purpose DMA (DMA) with up-to 12 channels - Event Request Unit (ERU) - Flexible CRC Engine (FCE) for multiple bit error detection On-Chip Memories - 16 KB boot ROM - 8 KB high-speed program memory - 12 KB high speed data memory - 128 KB Flash Memory with 1 KB instruction cache Communication Peripherals - Universal Serial Bus (USB), USB 2.0 device, with integrated PHY - Controller Area Network interface (MultiCAN), Full-CAN/Basic-CAN with 2 nodes - 4 Universal Serial Interface Channels (USIC) usable as UART, double-SPI, quad-SPI, IIC, IIS, LIN interfaces - LED and Touch-Sense Controller (LEDTS) Analog Frontend Peripherals - 2 Analog-Digital Converters (VADC) - Digital-Analogue Converter (DAC) Industrial Control Peripherals - 2 Capture/Compare Units 4 (CCU4) - 1 Capture/Compare Units 8 (CCU8) - 4 High Resolution PWM (HRPWM) channels - 1 Position Interfaces (POSIF) - Window Watchdog Timer (WDT) - Die Temperature Sensor (DTS) - Real Time Clock module with alarm support - System Control Unit (SCU) for system configuration and control Input/Output Lines - Programmable port driver control module (PORTS) - Individually bit addressable - Tri-stated in input mode - Push/pull or open drain output mode - Boundary scan test support over JTAG interface On-Chip Debug Support - Full support for debug features: 8 breakpoints, CoreSight, trace - Various interfaces: ARM-JTAG, SWD, single wire trace.

[Chip Vendor] [Distributors]

Development Tools
Compiler, Assembler, Linker, Debugger
JTAG Debuggers
Data Sheets
Data Sheet
1,409,966 bytes
Generic User Guide
1,755,988 bytes
Technical Reference Manual
935,507 bytes
User Manual
17,065,723 bytes

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Header Files
FLASH Utilities
Real-Time OS
Simulated Features
NOTE
Simulation for this device is provided by the default peripheral simulation driver.

Complete peripheral simulation is not available and is not planned to be implemented by ARM.

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