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Freescale Semiconductor MK21DN512xxx5

The Freescale Semiconductor MK21DN512xxx5 is a Core features - 32-bit ARM Cortex-M4 core (up to 50MHz CPU Clock) - DSP Support - Nested vectored interrupt contr. (NVIC) - Async. wake-up interrupt contr. (AWIC) Debug & trace capability - 2-pin serial wire debug (SWD) - IEEE 1149.1 Joint Test Action Group (JTAG) - IEEE 1149.7 compact JTAG (cJTAG) - Trace port interface unit (TPIU) - Flash patch and breakpoint (FPB) - Data watchpoint and trace (DWT) - Instrumentation trace macrocell (ITM) System and power management - SW/HW watchdog with external monitor pin - DMA controller - Low-leakage wake-up unit (LLWU) - Power management contr. with 10 different power modes - Non-maskable interrupt (NMI) - 128-bit unique identification (ID) number per chip Clocks - Multi-purpose clock generator - PLL and FLL operation - Internal reference clocks - 3MHz to 32MHz crystal osc. - 32kHz crystal osc. Memories and Memory Interfaces - 512KB Flash - 64KB SRAM - Flash security and protection features - Serial flash programming interface (EzPort) Security and integrity - Cyclic redundancy check (CRC) Analog - 16-bit SAR ADC - Programmable voltage reference (VREF) - High-speed Analog comparator (CMP) with 6-bit DAC Timers - 1x8ch motor control/general purpose/PWM flexible timer (FTM) - 1x2ch quadrature decoder/general purpose/PWM flexible timer (FTM) - Carrier modulator timer (CMT) - Programmable delay block (PDB) - 1x4ch programmable interrupt timer (PIT) - Low-power timer (LPT) Communications - SPI - I2C with SMBUS support - UART (w/ ISO7816, IrDA and HW flow control) Human-machine interface - up to 44 GPIO Pin (pin interrupt support, DMA request capability) - Capacitive touch sensing inputs.


Development Tools
Compiler, Assembler, Linker, Debugger
JTAG Debuggers
Data Sheets
Data Sheet
1,509,109 bytes
Generic User Guide
1,755,988 bytes
Technical Reference Manual
935,507 bytes

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FLASH Utilities
Real-Time OS
Simulated Features
Simulation for this device is provided by the default peripheral simulation driver.

Complete peripheral simulation is not available and is not planned to be implemented by ARM.

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