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STMicroelectronics STM32F373C8

The STMicroelectronics STM32F373C8 is a Core - ARM 32-bit Cortex-M4 CPU with FPU - single-cycle multiplication and HW division - DSP instruction - 72 MHz maximum frequency Memories - 64 to 256 Kbytes of Flash memory - 32 Kbytes of SRAM with HW parity check CRC calculation unit Reset and power management - Voltage range: 2.0 to 3.6 V - Power-on/Power down reset (POR/PDR) - Programmable voltage detector (PVD) - Low power modes: Sleep, Stop, Standby - VBAT supply for RTC and backup registers Clock management - 4 to 32 MHz crystal oscillator - 32 kHz oscillator for RTC with calibration - Internal 8 MHz RC with x16 PLL option - Internal 40 kHz oscillator Up to 84 fast I/Os - All mappable on external interrupt vectors - Up to 45 I/Os with 5 V tolerant capability 12-channel DMA controller 1 12-bit, 1.0 us ADC (up to 16 channels) 3 16-bit Sigma Delta ADC 3 12-bit DAC channels 2 fast rail-to-rail analog comparators with programmable input and output Up to 24 capacitive sensing channels 17 timers - 2 32-bit timers and 3 16-bit timers with up to 4 IC/OC/PWM or pulse counters - 2 16-bit timers with up to 2 IC/OC/PWM or pulse counters - 4 16-bit timers with up to 1 IC/OC/PWM or pulse counter - Independent and system watchdog timers - SysTick timer: 24-bit downcounter - 3 16-bit basic timers to drive the DAC Calendar RTC with Alarm and periodic wakeup from Stop/Standby Communication interfaces - CAN interface (2.0B Active) - 2 I2Cs supporting Fast Mode Plus (1 Mbit/s) - 3 USARTs supporting synchronous mode, modem control, ISO/IEC 7816, LIN, IrDA - 3 SPIs (18 Mbit/s), muxed I2S - HDMI-CEC bus interface - USB 2.0 full speed interface Serial wire devices, JTAG, Cortex-M4 ETM 96-bit unique ID.


Development Tools
Compiler, Assembler, Linker, Debugger
JTAG Debuggers
Data Sheets
1,865,357 bytes
Generic User Guide
1,755,988 bytes
Reference Manual
12,793,020 bytes
Technical Reference Manual
935,507 bytes

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Header Files
FLASH Utilities
Real-Time OS
Simulated Features
Simulation for this device is provided by the default peripheral simulation driver.

Complete peripheral simulation is not available and is not planned to be implemented by ARM.

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