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STMicroelectronics STM32F372RC

The STMicroelectronics STM32F372RC is a Core - ARM 32-bit Cortex-M4 CPU - 72 MHz max. frequency, 1.25 DMIPS/MHz - FPU (floating-point unit) - MPU (memory protection unit) Memories - 64 to 256 Kbytes of Flash memory - Up to 32 Kbytes of SRAM with HW parity check Clock management - 4 to 32 MHz crystal oscillator - 32 kHz oscillator for RTC with calibration - Internal 8 MHz RC with x 16 PLL option - Internal 40 kHz oscillator Calendar RTC - Alarm, periodic wakeup from Stop/Standby Reset and supply management - 2.0 to 3.6 V - POR, PDR and PVD Low power - Sleep, Stop, and Standby modes - VBAT supply for RTC and backup registers Debug mode - serial wire debug (SWD), JTAG - Cortex-M4 ETM DMA - 12-channel DMA controller - Peripherals supported: timers, ADCs, SPIs, I2Cs, USARTs and DACs Up to 3 x 16-bit Sigma Delta ADC, up to 19 single/ 10 diff channels 1 x 12-bit, 1 us ADC with separate analog supply from 2.4 V to 3.6 V Up to 2 fast rail-to-rail analog comparators Temperature sensor Up to 3 x 12-bit DACs Support for up to 18 capacitive sensing keys Up to 84 fast I/O ports - mappable on external interrupt vectors - several 5 V-tolerant 14 timers - 2 x 32-bit timer and 3 x 16-bit timers - 2 x 16-bit timers with up to 2 IC/OC/PWM or pulse counter - 4 x 16-bit timers with up to 1 IC/OC/PWM or pulse counter - 2 x watchdog timers (independent, window) - SysTick timer: 24-bit downcounter - 3 x 16-bit basic timers to drive the DAC Communication interfaces - CAN interface (2.0B Active) - USB 2.0 full speed interface - 2 x I2C with 20 mA current sink to support Fast mode plus - Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control). - Up to 3 SPIs, with muxed I2S - CRC calculation unit, 96-bit unique ID - CEC bus interface.


Development Tools
Compiler, Assembler, Linker, Debugger
JTAG Debuggers
Data Sheets
1,959,801 bytes
Generic User Guide
1,755,988 bytes
Reference Manual
12,718,509 bytes
Technical Reference Manual
935,507 bytes

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Header Files
FLASH Utilities
Real-Time OS
Simulated Features
Simulation for this device is provided by the default peripheral simulation driver.

Complete peripheral simulation is not available and is not planned to be implemented by ARM.

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