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Spansion MB9AF111M

The Spansion MB9AF111M is a 32-bit ARM Cortex-M3 Core (r2p1) - Up to 40MHz Frequency Operation - Nested Vectored Interrupt Controller (NVIC) - 24-bit System timer (SysTick) On-chip Memories - 64 Kbyte Flash - 8 Kbyte SRAM for high-performance CPU - 8 Kbyte SRAM for CPU/DMA Controller External Bus Interface - Supports SRAM, NOR Flash device - Up to 8 chip selects - 8/16-bit Data width - Up to 25-bit Address bit - Suports Address/Data multiplex Multi-function Serial Interface (Max. 8channels) - UART, CSIO, LIN, I2C DMA Controller (8channels) A/D Converter (Max. 16channels) - 12-bit A/D Converter - Built-in 3unit Base Timer (Max. 8channels) - Operation mode: 16-bit PWM, 16-bit PPG, 16/32-bit reload, 16/32-bit PWC General Purpose I/O Port - 66 fast I/O Ports Multi-function Timer (Max. 2unit) Quadrature Position/Revolution Counter (QPRC) (Max. 2unit) Dual Timer (Two 32/16bit Down Counter) Watch Counter External Interrupt Controller Unit - Up to 16 external vectors - Inc. non-maskable interrupt(NMI) Watchdog Timer (2channels) CRC (Cyclic Redundancy Check) Accelerator Clock and Reset - 5 clock sources (2 ext. osc, 2 CR osc, and PLL) - Reset sources: INITX Pins, POR, SW, Watchdog, LVD, CSV Clock Super Visor (CSV) - Ext. OSC clock failure (clock stop) detect - Ext. OSC frequency anomaly detect Low Voltage Detector (LVD) - LVD1: error reporting via interrupt - LVD2: auto-reset operation Low Power Mode - 3 power saving modes (SLEEP, TIMER, STOP) Debug - Serial Wire JTAG Debug Port (SWJ-DP).

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Development Tools
Compiler, Assembler, Linker, Debugger
Evaluation Boards
JTAG Debuggers
Data Sheets
1,147,280 bytes
Generic User Guide
1,364,135 bytes
Technical Reference Manual
1,106,603 bytes

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Header Files
FLASH Utilities
Device Programmers
Real-Time OS
Simulated Features
Simulation for this device is provided by the default peripheral simulation driver.

Complete peripheral simulation is not available and is not planned to be implemented by ARM.

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